dunedaq::timing::MasterMuxDesign Class Reference

Class for PDI timing master design on mux board. More...

#include <MasterMuxDesign.hpp>

Inheritance diagram for dunedaq::timing::MasterMuxDesign:

Collaboration diagram for dunedaq::timing::MasterMuxDesign:

Public Member Functions
	MasterMuxDesign (const uhal::Node &node)
virtual	~MasterMuxDesign ()
std::string	get_status (bool print_out=false) const override
	Get status string, optionally print.
uint32_t	measure_endpoint_rtt (uint32_t address, bool control_sfp=true, int sfp_mux=-1) const override
	Measure the endpoint round trip time.
void	apply_endpoint_delay (uint32_t address, uint32_t coarse_delay, uint32_t fine_delay, uint32_t phase_delay, bool measure_rtt=false, bool control_sfp=true, int sfp_mux=-1) const override
	Apply delay to endpoint.
std::vector< uint32_t >	scan_sfp_mux () const override
	Scan SFP for alive timing transmitters.
void	resync_active_cdr () const override
	Resync active cdr.
Public Member Functions inherited from dunedaq::timing::SFPMuxDesignInterface
	SFPMuxDesignInterface (const uhal::Node &node)
virtual	~SFPMuxDesignInterface ()
void	switch_mux (uint8_t mux_channel, bool resync_cdr=false) const override
	Switch the SFP mux channel.
uint8_t	read_active_mux () const override
	Read the active SFP mux channel.
Public Member Functions inherited from dunedaq::timing::MuxDesignInterface
	MuxDesignInterface (const uhal::Node &node)
virtual	~MuxDesignInterface ()
Public Member Functions inherited from dunedaq::timing::TopDesignInterface
	TopDesignInterface (const uhal::Node &node)
virtual	~TopDesignInterface ()
template<class IO >
const IO *	get_io_node () const
Public Member Functions inherited from dunedaq::timing::TimingNode
	TimingNode (const uhal::Node &node)
virtual	~TimingNode ()
std::map< std::string, uhal::ValWord< uint32_t > >	read_sub_nodes (const uhal::Node &node, bool dispatch=true) const
	Read subnodes.
void	reset_sub_nodes (const uhal::Node &node, uint32_t aValue=0x0, bool dispatch=true) const
	Reset subnodes.
Public Member Functions inherited from dunedaq::timing::MasterDesign
	MasterDesign (const uhal::Node &node)
virtual	~MasterDesign ()
void	configure (ClockSource clock_source, TimestampSource ts_source) const override
	Prepare the timing master for data taking.
uint64_t	read_master_timestamp () const override
	Read the current timestamp.
void	sync_timestamp (TimestampSource source) const override
	Sync timestamp to current machine value.
void	enable_periodic_fl_cmd (uint32_t channel, double rate, bool poisson=false) const override
	Configure fake trigger generator.
void	enable_periodic_fl_cmd (uint32_t command, uint32_t channel, double rate, bool poisson=false) const override
	Configure fake trigger generator.
const MasterNodeInterface *	get_master_node_plain () const override
	Get master node pointer.
uint32_t	read_firmware_version () const override
	Read master firmware version.
void	validate_firmware_version () const override
	Validate master firmware version.
void	get_info (timingfirmwareinfo::TimingDeviceInfo &mon_data) const override
	Give info to collector.
void	get_info (timingfirmwareinfo::MasterMonitorData &mon_data) const override
	Give info to collector.
Public Member Functions inherited from dunedaq::timing::TopDesign
	TopDesign (const uhal::Node &node)
virtual	~TopDesign ()
const IONode *	get_io_node_plain () const override
	Get io node pointer.
void	soft_reset_io () const override
	Reset timing node.
void	reset_io (const std::string &clock_config_file) const override
	Reset timing node.
void	reset_io (const ClockSource &clock_source) const override
	Reset timing node.
void	configure (ClockSource clock_source) const override
	Prepare the timing device for data taking.
std::string	get_hardware_info (bool print_out=false) const override
	Print hardware information.
void	get_info (timingfirmwareinfo::TimingDeviceInfo &mon_data) const override
	Give info to collector.
Public Member Functions inherited from dunedaq::timing::MasterDesignInterface
	MasterDesignInterface (const uhal::Node &node)
virtual	~MasterDesignInterface ()
template<class MST >
const MST *	get_master_node () const
virtual void	get_info (timingfirmwareinfo::TimingDeviceInfo &mon_data) const=0
	Give info to collector.

Detailed Description

Class for PDI timing master design on mux board.

Definition at line 34 of file MasterMuxDesign.hpp.

Constructor & Destructor Documentation

MasterMuxDesign()

dunedaq::timing::MasterMuxDesign::MasterMuxDesign ( const uhal::Node & node )

explicit

Definition at line 11 of file MasterMuxDesign.cpp.

  : TopDesignInterface(node)
  , MuxDesignInterface(node)
  , MasterDesignInterface(node)
  , SFPMuxDesignInterface(node)
  , MasterDesign(node)
{}

~MasterMuxDesign()

dunedaq::timing::MasterMuxDesign::~MasterMuxDesign ( )

virtual

Definition at line 21 of file MasterMuxDesign.cpp.

{}

Member Function Documentation

apply_endpoint_delay()

void dunedaq::timing::MasterMuxDesign::apply_endpoint_delay ( uint32_t address, uint32_t coarse_delay, uint32_t fine_delay, uint32_t phase_delay, bool measure_rtt = false, bool control_sfp = true, int sfp_mux = -1 ) const

overridevirtual

Apply delay to endpoint.

Reimplemented from dunedaq::timing::MasterDesign.

Definition at line 61 of file MasterMuxDesign.cpp.

{
  if (sfp_mux > -1)
  {
    if (control_sfp && measure_rtt)
    {
      // set fanout rtt mux channel, and do not wait for fanout rtt ept to be in a good state
      switch_mux(sfp_mux);
    }
    // gets master rtt ept in a good state, and sends echo command
    get_master_node_plain()->apply_endpoint_delay(address, coarse_delay, fine_delay, phase_delay, measure_rtt, control_sfp);
  }
  else
  {
    get_master_node_plain()->apply_endpoint_delay(address, coarse_delay, fine_delay, phase_delay, measure_rtt, control_sfp);
  }
}

get_status()

std::string dunedaq::timing::MasterMuxDesign::get_status ( bool print_out = false ) const

overridevirtual

Get status string, optionally print.

Implements dunedaq::timing::TimingNode.

Reimplemented in dunedaq::timing::OuroborosMuxDesign.

Definition at line 27 of file MasterMuxDesign.cpp.

{
  std::stringstream status;
  status << get_io_node_plain()->get_pll_status();
  status << get_master_node_plain()->get_status();
  // TODO mux specific status
  if (print_out)
    TLOG() << status.str();
  return status.str();
}

measure_endpoint_rtt()

uint32_t dunedaq::timing::MasterMuxDesign::measure_endpoint_rtt ( uint32_t address, bool control_sfp = true, int sfp_mux = -1 ) const

overridevirtual

Measure the endpoint round trip time.

Returns

{ description_of_the_return_value }

Reimplemented from dunedaq::timing::MasterDesign.

Definition at line 41 of file MasterMuxDesign.cpp.

{
 
  if (sfp_mux > -1) {
    if (control_sfp) 
    {
      // set fanout rtt mux channel, and do not wait for fanout rtt ept to be in a good state
      switch_mux(sfp_mux);
    }
    // gets master rtt ept in a good state, and sends echo command
    uint32_t rtt = get_master_node_plain()->measure_endpoint_rtt(address, control_sfp);
    return rtt;
  } else {
    return get_master_node_plain()->measure_endpoint_rtt(address, control_sfp);
  }
}

resync_active_cdr()

void dunedaq::timing::MasterMuxDesign::resync_active_cdr ( ) const

overridevirtual

Resync active cdr.

Returns

{ description_of_the_return_value }

Implements dunedaq::timing::MuxDesignInterface.

Definition at line 122 of file MasterMuxDesign.cpp.

{
  this->get_master_node_plain()->enable_upstream_endpoint();
}

scan_sfp_mux()

std::vector< uint32_t > dunedaq::timing::MasterMuxDesign::scan_sfp_mux ( ) const

overridevirtual

Scan SFP for alive timing transmitters.

Implements dunedaq::timing::SFPMuxDesignInterface.

Definition at line 88 of file MasterMuxDesign.cpp.

{
  std::vector<uint32_t> locked_channels;
 
  // TODO will this be right for every fanout board, need to check the IO board
  uint32_t number_of_mux_channels = 8;
  for (uint32_t i = 0; i < number_of_mux_channels; ++i)
  {
    TLOG_DEBUG(0) << "Scanning slot " << i;
 
    try
    {
      switch_mux(i);
      this->get_master_node_plain()->enable_upstream_endpoint();
    } catch (...) {
      TLOG_DEBUG(0) << "Slot " << i << " not locked";
    }
    // TODO catch right except
 
    TLOG_DEBUG(0) << "Slot " << i << " locked";
    locked_channels.push_back(i);
  }
 
  if (locked_channels.size()) {
    TLOG() << "Slots locked: " << vec_fmt(locked_channels);
  } else {
    TLOG() << "No slots locked";
  }
  return locked_channels;
}

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The documentation for this class was generated from the following files:

• /github/workspace/dunedaq/sourcecode/timing/include/timing/MasterMuxDesign.hpp
• /github/workspace/dunedaq/sourcecode/timing/src/MasterMuxDesign.cpp