12#ifndef TIMING_INCLUDE_TIMING_MASTERDESIGNINTERFACE_HPP_
13#define TIMING_INCLUDE_TIMING_MASTERDESIGNINTERFACE_HPP_
21#include "uhal/DerivedNode.hpp"
62 bool control_sfp =
true,
63 int sfp_mux = -1)
const = 0;
68 uint32_t coarse_delay,
71 bool measure_rtt =
false,
72 bool control_sfp =
true,
73 int sfp_mux = -1)
const = 0;
82 virtual void enable_periodic_fl_cmd(uint32_t command, uint32_t channel,
double rate,
bool poisson =
false)
const = 0;
Base class for timing master designs.
virtual void get_info(timingfirmwareinfo::MasterMonitorData &mon_data) const =0
Give info to collector.
const MST * get_master_node() const
MasterDesignInterface(const uhal::Node &node)
virtual void sync_timestamp(TimestampSource source) const =0
Sync timestamp to current machine value.
virtual uint32_t measure_endpoint_rtt(uint32_t address, bool control_sfp=true, int sfp_mux=-1) const =0
Measure the endpoint round trip time.
virtual void configure(ClockSource clock_source, TimestampSource ts_source) const =0
Prepare the timing device for data taking.
virtual void enable_periodic_fl_cmd(uint32_t command, uint32_t channel, double rate, bool poisson=false) const =0
Configure fake trigger generator.
virtual const MasterNodeInterface * get_master_node_plain() const =0
Get master node pointer.
virtual ~MasterDesignInterface()
virtual void enable_periodic_fl_cmd(uint32_t channel, double rate, bool poisson=false) const =0
Configure fake trigger generator.
virtual void apply_endpoint_delay(uint32_t address, uint32_t coarse_delay, uint32_t fine_delay, uint32_t phase_delay, bool measure_rtt=false, bool control_sfp=true, int sfp_mux=-1) const =0
Apply delay to endpoint.
virtual uint64_t read_master_timestamp() const =0
Read the current timestamp.
Base class for timing IO nodes.
Base class for timing top design nodes.
virtual void configure(ClockSource clock_source) const =0
Prepare the timing device for data taking.
virtual void get_info(timingfirmwareinfo::TimingDeviceInfo &mon_data) const =0
Give info to collector.