94 def reset(self, soft, forcepllcfg):
95 '''
96 Perform a hard reset on the timing master, including
97
98 \b
99 - ipbus registers
100 - i2c buses
101 - pll and pll configuration
102
103 \b
104 Fanout mode:
105 0 = local master
106 1 = sfp
107 '''
108
109 echo('Resetting ' + click.style(self.device.id(), fg='blue'))
110
111 lDevice = self.device
112 lBoardType = self.info.boardType
113 lCarrierType = self.info.carrierType
114 lDesignType = self.info.designType
115
116 lIO = lDevice.getNode('io')
117
118
119 self.soft_reset()
120
121 if not soft:
122 time.sleep(0.1)
123
124
125 self.resetI2CnPll()
126
127
128 self.enableI2CSwitch()
129
130 lUniqueID = self.readUID()
131
132
133
134 try:
135 lRevision = self.kUIDRevisionMap[lUniqueID]
136 except KeyError:
137 raise click.ClickException("No revision associated to UID "+hex(lUniqueID))
138
139
140 lSIChip = self.getSIChipSlave()
141
142
143 if forcepllcfg is not None:
144 lFullClockConfigPath = forcepllcfg
145 echo("Using PLL Clock configuration file: "+style(basename(lFullClockConfigPath), fg='green') )
146
147 else:
148 try:
149 lClockConfigPath = self.kClockConfigMap[lRevision]
150 except KeyError:
151 raise ClickException("Board revision " << lRevision << " has no associated clock configuration")
152
153
154 echo("PLL Clock configuration file: "+style(lClockConfigPath, fg='green') )
155
156
157 lFullClockConfigPath = expandvars(join('${TIMING_SHARE}/config/etc/clock', lClockConfigPath))
158
159 lSIChip.configure(lFullClockConfigPath)
160 echo("SI354x configuration id: {}".format(style(lSIChip.read_config_id(), fg='green')))
161
162
163