| apply_endpoint_delay(uint32_t address, uint32_t coarse_delay, uint32_t fine_delay, uint32_t phase_delay, bool measure_rtt=false, bool control_sfp=true, int sfp_mux=-1) const =0 | dunedaq::timing::MasterDesignInterface | pure virtual |
| configure(ClockSource clock_source, TimestampSource ts_source) const =0 | dunedaq::timing::MasterDesignInterface | pure virtual |
| configure(ClockSource clock_source) const=0 | dunedaq::timing::MasterDesignInterface | privatevirtual |
| enable_periodic_fl_cmd(uint32_t channel, double rate, bool poisson=false) const =0 | dunedaq::timing::MasterDesignInterface | pure virtual |
| enable_periodic_fl_cmd(uint32_t command, uint32_t channel, double rate, bool poisson=false) const =0 | dunedaq::timing::MasterDesignInterface | pure virtual |
| get_hardware_info(bool print_out=false) const =0 | dunedaq::timing::TopDesignInterface | pure virtual |
| get_info(timingfirmwareinfo::MasterMonitorData &mon_data) const =0 | dunedaq::timing::MasterDesignInterface | pure virtual |
| get_info(timingfirmwareinfo::TimingDeviceInfo &mon_data) const=0 | dunedaq::timing::MasterDesignInterface | virtual |
| get_io_node() const | dunedaq::timing::TopDesignInterface | inline |
| get_io_node_plain() const =0 | dunedaq::timing::TopDesignInterface | pure virtual |
| get_master_node() const | dunedaq::timing::MasterDesignInterface | inline |
| get_master_node_plain() const =0 | dunedaq::timing::MasterDesignInterface | pure virtual |
| get_status(bool print_out=false) const =0 | dunedaq::timing::TimingNode | pure virtual |
| MasterDesignInterface(const uhal::Node &node) | dunedaq::timing::MasterDesignInterface | inlineexplicit |
| measure_endpoint_rtt(uint32_t address, bool control_sfp=true, int sfp_mux=-1) const =0 | dunedaq::timing::MasterDesignInterface | pure virtual |
| read_firmware_version() const =0 | dunedaq::timing::TopDesignInterface | pure virtual |
| read_master_timestamp() const =0 | dunedaq::timing::MasterDesignInterface | pure virtual |
| read_sub_nodes(const uhal::Node &node, bool dispatch=true) const | dunedaq::timing::TimingNode | |
| reset_io(const std::string &clock_config_file) const =0 | dunedaq::timing::TopDesignInterface | pure virtual |
| reset_io(const ClockSource &clock_source) const =0 | dunedaq::timing::TopDesignInterface | pure virtual |
| reset_sub_nodes(const uhal::Node &node, uint32_t aValue=0x0, bool dispatch=true) const | dunedaq::timing::TimingNode | |
| soft_reset_io() const =0 | dunedaq::timing::TopDesignInterface | pure virtual |
| sync_timestamp(TimestampSource source) const =0 | dunedaq::timing::MasterDesignInterface | pure virtual |
| TimingNode(const uhal::Node &node) | dunedaq::timing::TimingNode | explicit |
| TopDesignInterface(const uhal::Node &node) | dunedaq::timing::TopDesignInterface | inlineexplicit |
| validate_firmware_version() const =0 | dunedaq::timing::TopDesignInterface | pure virtual |
| ~MasterDesignInterface() | dunedaq::timing::MasterDesignInterface | inlinevirtual |
| ~TimingNode() | dunedaq::timing::TimingNode | virtual |
| ~TopDesignInterface() | dunedaq::timing::TopDesignInterface | inlinevirtual |
1.12.0