dunedaq::timing::FLCmdGeneratorNode Class Reference

Class for master global node. More...

#include <FLCmdGeneratorNode.hpp>

Inheritance diagram for dunedaq::timing::FLCmdGeneratorNode:

Collaboration diagram for dunedaq::timing::FLCmdGeneratorNode:

Public Member Functions
	FLCmdGeneratorNode (const uhal::Node &node)
virtual	~FLCmdGeneratorNode ()
std::string	get_status (bool print_out=false) const override
	Get status string, optionally print.
virtual void	send_fl_cmd (uint32_t command, uint32_t channel) const
	Send a fixed length command.
void	enable_periodic_fl_cmd (uint32_t channel, double rate, bool poisson, uint32_t clock_frequency_hz) const
	Configure fake trigger.
void	enable_periodic_fl_cmd (uint32_t command, uint32_t channel, double rate, bool poisson, uint32_t clock_frequency_hz) const
	Configure fake trigger.
void	enable_periodic_fl_cmd (uint32_t channel, uint32_t divisor, uint32_t prescale, bool poisson) const
	Configure fake trigger.
void	enable_periodic_fl_cmd (uint32_t command, uint32_t channel, uint32_t divisor, uint32_t prescale, bool poisson) const
	Configure fake trigger.
void	disable_fake_trigger (uint32_t channel) const
	Clear fake trigger configuration.
std::string	get_cmd_counters_table (bool print_out=false) const
	Get command counters status string.
Public Member Functions inherited from dunedaq::timing::TimingNode
	TimingNode (const uhal::Node &node)
virtual	~TimingNode ()
std::map< std::string, uhal::ValWord< uint32_t > >	read_sub_nodes (const uhal::Node &node, bool dispatch=true) const
	Read subnodes.
void	reset_sub_nodes (const uhal::Node &node, uint32_t aValue=0x0, bool dispatch=true) const
	Reset subnodes.

Static Public Member Functions
static void	parse_periodic_fl_cmd_rate (double requested_rate, uint32_t clock_frequency_hz, double &actual_rate, uint32_t &divisor, uint32_t &prescale)

Private Member Functions
void	validate_command (uint32_t command) const
void	validate_channel (uint32_t channel) const

Detailed Description

Class for master global node.

Definition at line 32 of file FLCmdGeneratorNode.hpp.

Constructor & Destructor Documentation

FLCmdGeneratorNode()

dunedaq::timing::FLCmdGeneratorNode::FLCmdGeneratorNode ( const uhal::Node & node )

explicit

Definition at line 23 of file FLCmdGeneratorNode.cpp.

  : TimingNode(node)
{}

~FLCmdGeneratorNode()

dunedaq::timing::FLCmdGeneratorNode::~FLCmdGeneratorNode ( )

virtual

Definition at line 29 of file FLCmdGeneratorNode.cpp.

{}

Member Function Documentation

disable_fake_trigger()

void dunedaq::timing::FLCmdGeneratorNode::disable_fake_trigger

(

uint32_t

channel

)

const

Clear fake trigger configuration.

Definition at line 170 of file FLCmdGeneratorNode.cpp.

{
  validate_channel(channel);
 
  // Clear the internal trigger generator.
  getNode("sel").write(channel);
  reset_sub_nodes(getNode("chan_ctrl"));
  TLOG() << "Fake trigger generator " << format_reg_value(channel) << " configuration cleared";
}

enable_periodic_fl_cmd() [1/4]

void dunedaq::timing::FLCmdGeneratorNode::enable_periodic_fl_cmd	(	uint32_t	channel,
		double	rate,
		bool	poisson,
		uint32_t	clock_frequency_hz ) const

Configure fake trigger.

Definition at line 90 of file FLCmdGeneratorNode.cpp.

{
  enable_periodic_fl_cmd(0x8+channel, channel, rate, poisson, clock_frequency_hz);
}

enable_periodic_fl_cmd() [2/4]

void dunedaq::timing::FLCmdGeneratorNode::enable_periodic_fl_cmd	(	uint32_t	channel,
		uint32_t	divisor,
		uint32_t	prescale,
		bool	poisson ) const

Configure fake trigger.

Definition at line 137 of file FLCmdGeneratorNode.cpp.

{
  enable_periodic_fl_cmd(0x8+channel, channel, divisor, prescale, poisson);
}

enable_periodic_fl_cmd() [3/4]

void dunedaq::timing::FLCmdGeneratorNode::enable_periodic_fl_cmd	(	uint32_t	command,
		uint32_t	channel,
		double	rate,
		bool	poisson,
		uint32_t	clock_frequency_hz ) const

Configure fake trigger.

Definition at line 101 of file FLCmdGeneratorNode.cpp.

{
  uint32_t divisor;
  uint32_t prescale;
  double actual_rate;
 
  parse_periodic_fl_cmd_rate(rate, clock_frequency_hz, actual_rate, divisor, prescale);
 
  TLOG() << "Requested rate, actual rate: " << rate << ", " << actual_rate;
  TLOG() << "prescale, divisor: " << prescale << ", " << divisor;
 
  std::stringstream trig_stream;
  trig_stream << "> Periodic rate for command 0x" << std::hex << command << ", on channel 0x" << channel
              << " set to " << std::setprecision(3) << std::scientific << actual_rate << " Hz";
  TLOG() << trig_stream.str();
 
  std::stringstream trigger_mode_stream;
  trigger_mode_stream << "> Trigger mode: ";
 
  if (poisson) {
    trigger_mode_stream << "poisson";
  } else {
    trigger_mode_stream << "periodic";
  }
  TLOG() << trigger_mode_stream.str();
  enable_periodic_fl_cmd(command, channel, divisor, prescale, poisson);
 
}

enable_periodic_fl_cmd() [4/4]

void dunedaq::timing::FLCmdGeneratorNode::enable_periodic_fl_cmd	(	uint32_t	command,
		uint32_t	channel,
		uint32_t	divisor,
		uint32_t	prescale,
		bool	poisson ) const

Configure fake trigger.

Definition at line 148 of file FLCmdGeneratorNode.cpp.

{
  validate_command(command);
  validate_channel(channel);
 
  getNode("sel").write(channel);
 
  getNode("chan_ctrl.type").write(command);
  getNode("chan_ctrl.rate_div_d").write(divisor);
  getNode("chan_ctrl.rate_div_p").write(prescale);
  getNode("chan_ctrl.patt").write(poisson);
  getNode("chan_ctrl.en").write(1); // Start the command stream
  getClient().dispatch();
}

get_cmd_counters_table()

std::string dunedaq::timing::FLCmdGeneratorNode::get_cmd_counters_table

(

bool

print_out = false

)

const

Get command counters status string.

Definition at line 183 of file FLCmdGeneratorNode.cpp.

{
  std::stringstream counters_table;
  auto accepted_counters = getNode("actrs").readBlock(getNode("actrs").getSize());
  auto rejected_counters = getNode("rctrs").readBlock(getNode("actrs").getSize());
  getClient().dispatch();
 
  std::vector<uhal::ValVector<uint32_t>> counters_container = { accepted_counters, rejected_counters }; // NOLINT(build/unsigned)
 
  counters_table << format_counters_table(counters_container,
                                          { "Accept counters", "Reject counters" },
                                          "Cmd gen counters",
                                          { "0x0", "0x1", "0x2", "0x3", "0x4" },
                                          "Chan");
 
  if (print_out)
    TLOG() << counters_table.str();
  return counters_table.str();
}

get_status()

std::string dunedaq::timing::FLCmdGeneratorNode::get_status ( bool print_out = false ) const

overridevirtual

Get status string, optionally print.

Implements dunedaq::timing::TimingNode.

Definition at line 34 of file FLCmdGeneratorNode.cpp.

{
  std::stringstream status;
  auto subnodes = read_sub_nodes(getNode("csr.stat"));
  status << format_reg_table(subnodes, "FL Cmd gen state");
  if (print_out)
    TLOG() << status.str();
  return status.str();
}

parse_periodic_fl_cmd_rate()

void dunedaq::timing::FLCmdGeneratorNode::parse_periodic_fl_cmd_rate ( double requested_rate, uint32_t clock_frequency_hz, double & actual_rate, uint32_t & divisor, uint32_t & prescale )

static

Definition at line 231 of file FLCmdGeneratorNode.cpp.

{
  // Rate =  (clock_frequency_hz / 2^(d+8)) / p where n in [0,15] and p in [1,256]
 
  // DIVIDER (int): Frequency divider.
 
  // The division from clock_frequency_hz to the desired rate is done in three steps:
  // a) A pre-division by 256
  // b) Division by a power of two set by n = 2 ^ rate_div_d (ranging from 2^0 -> 2^15)
  // c) 1-in-n prescaling set by n = rate_div_p
 
  double div = ceil(log(clock_frequency_hz / (requested_rate * 256 * 256)) / log(2));
  if (div < 0) {
    divisor = 0;
  } else if (div > 15) {
    divisor = 15;
  } else {
    divisor = div;
  }
 
  uint32_t ps = (uint32_t)((clock_frequency_hz / (requested_rate * 256 * (1 << divisor))) + 0.5); // NOLINT(build/unsigned)
  if (ps == 0 || ps > 256)
  {
    throw BadRequestedFakeTriggerRate(ERS_HERE, requested_rate, ps);
  } else {
    prescale = ps;
  }
  actual_rate = static_cast<double>(clock_frequency_hz) / (256 * prescale * (1 << divisor));
}

send_fl_cmd()

void dunedaq::timing::FLCmdGeneratorNode::send_fl_cmd ( uint32_t command, uint32_t channel ) const

virtual

Send a fixed length command.

Definition at line 69 of file FLCmdGeneratorNode.cpp.

{
  validate_command(command);
  validate_channel(channel);
 
  getNode("sel").write(channel);
 
  reset_sub_nodes(getNode("chan_ctrl"));
 
  getNode("chan_ctrl.type").write(command);
  getNode("ctrl.force").write(0x1);
  getClient().dispatch();
 
  getNode("ctrl.force").write(0x0);
  getClient().dispatch();
}

validate_channel()

void dunedaq::timing::FLCmdGeneratorNode::validate_channel ( uint32_t channel ) const

private

Definition at line 58 of file FLCmdGeneratorNode.cpp.

{
  if (channel > 0x4)
  {
    throw InvalidFixedLatencyCommandChannel(ERS_HERE, channel);
  }
}

validate_command()

void dunedaq::timing::FLCmdGeneratorNode::validate_command ( uint32_t command ) const

private

Definition at line 47 of file FLCmdGeneratorNode.cpp.

{
  if (command > 0xff)
  {
    throw InvalidFixedLatencyCommand(ERS_HERE, command);
  }
}

---

The documentation for this class was generated from the following files:

• /github/workspace/dunedaq/sourcecode/timing/include/timing/FLCmdGeneratorNode.hpp
• /github/workspace/dunedaq/sourcecode/timing/src/FLCmdGeneratorNode.cpp