DUNE-DAQ
DUNE Trigger and Data Acquisition software
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Classes | Public Member Functions | Static Public Member Functions | Public Attributes | Private Member Functions | Private Attributes | List of all members
dunedaq::sspmodules::RegMap Class Reference

#include <RegMap.hpp>

Classes

class  Register
 

Public Member Functions

Register operator[] (std::string name)
 

Static Public Member Functions

static RegMap & Get ()
 

Public Attributes

unsigned int armStatus
 
unsigned int armError
 
unsigned int armCommand
 
unsigned int armVersion
 
unsigned int armTest [4]
 
unsigned int armRxAddress
 
unsigned int armRxCommand
 
unsigned int armRxSize
 
unsigned int armRxStatus
 
unsigned int armTxAddress
 
unsigned int armTxCommand
 
unsigned int armTxSize
 
unsigned int armTxStatus
 
unsigned int armPackets
 
unsigned int armOperMode
 
unsigned int armOptions
 
unsigned int armModemStatus
 
unsigned int PurgeDDR
 
unsigned int zynqTest [6]
 
unsigned int eventDataInterfaceSelect
 
unsigned int fakeNumEvents
 
unsigned int fakeEventSize
 
unsigned int fakeBaseline
 
unsigned int fakePeakSum
 
unsigned int fakePrerise
 
unsigned int timestamp [2]
 
unsigned int codeErrCounts [5]
 
unsigned int dispErrCounts [5]
 
unsigned int link_rx_status
 
unsigned int eventDataControl
 
unsigned int eventDataPhaseControl
 
unsigned int eventDataPhaseStatus
 
unsigned int c2c_master_status
 
unsigned int c2c_control
 
unsigned int c2c_master_intr_control
 
unsigned int dspStatus
 
unsigned int comm_clock_status
 
unsigned int comm_clock_control
 
unsigned int comm_led_config
 
unsigned int comm_led_input
 
unsigned int eventDataStatus
 
unsigned int qi_dac_control
 
unsigned int qi_dac_config
 
unsigned int bias_control
 
unsigned int bias_status
 
unsigned int bias_config [12]
 
unsigned int bias_readback [12]
 
unsigned int vmon_config
 
unsigned int vmon_select
 
unsigned int vmon_gpio
 
unsigned int vmon_config_readback
 
unsigned int vmon_select_readback
 
unsigned int vmon_gpio_readback
 
unsigned int vmon_id_readback
 
unsigned int vmon_control
 
unsigned int vmon_status
 
unsigned int vmon_bias [12]
 
unsigned int vmon_value [9]
 
unsigned int imon_config
 
unsigned int imon_select
 
unsigned int imon_gpio
 
unsigned int imon_config_readback
 
unsigned int imon_select_readback
 
unsigned int imon_gpio_readback
 
unsigned int imon_id_readback
 
unsigned int imon_control
 
unsigned int imon_status
 
unsigned int imon_bias [12]
 
unsigned int imon_value [9]
 
unsigned int board_id
 
unsigned int fifo_control
 
unsigned int dp_fpga_fw_build
 
unsigned int calib_build
 
unsigned int dp_clock_status
 
unsigned int module_id
 
unsigned int c2c_slave_status
 
unsigned int c2c_slave_intr_control
 
unsigned int channel_control [12]
 
unsigned int led_threshold [12]
 
unsigned int cfd_parameters [12]
 
unsigned int readout_pretrigger [12]
 
unsigned int readout_window [12]
 
unsigned int p_window [12]
 
unsigned int i2_window [12]
 
unsigned int m1_window [12]
 
unsigned int m2_window [12]
 
unsigned int d_window [12]
 
unsigned int i1_window [12]
 
unsigned int disc_width [12]
 
unsigned int baseline_start [12]
 
unsigned int c_window [12]
 
unsigned int trigger_input_delay
 
unsigned int gpio_output_width
 
unsigned int front_panel_config
 
unsigned int channel_pulsed_control
 
unsigned int dsp_led_config
 
unsigned int dsp_led_input
 
unsigned int baseline_delay
 
unsigned int diag_channel_input
 
unsigned int event_data_control
 
unsigned int adc_config
 
unsigned int adc_config_load
 
unsigned int qi_config
 
unsigned int qi_delay
 
unsigned int qi_pulse_width
 
unsigned int qi_pulsed
 
unsigned int external_gate_width
 
unsigned int pdts_cmd_control [3]
 
unsigned int lat_timestamp_lsb
 
unsigned int lat_timestamp_msb
 
unsigned int live_timestamp_lsb
 
unsigned int live_timestamp_msb
 
unsigned int sync_period
 
unsigned int sync_delay
 
unsigned int sync_count
 
unsigned int pdts_control
 
unsigned int pdts_status
 
unsigned int pdts_ts_preset [2]
 
unsigned int master_logic_control
 
unsigned int master_logic_status
 
unsigned int overflow_status
 
unsigned int phase_value
 
unsigned int link_tx_status
 
unsigned int dsp_clock_control
 
unsigned int dsp_clock_phase_control
 
unsigned int code_revision
 
unsigned int code_date
 
unsigned int dropped_event_count [12]
 
unsigned int accepted_event_count [12]
 
unsigned int ahit_count [12]
 
unsigned int disc_count [12]
 
unsigned int idelay_count [12]
 
unsigned int adc_data_monitor [12]
 
unsigned int adc_status [12]
 

Private Member Functions

 RegMap ()
 
 ~RegMap ()
 
 RegMap (RegMap const &)=delete
 
void operator= (RegMap const &)=delete
 
 RegMap (RegMap &&)=delete
 
RegMap & operator= (RegMap &&)=delete
 

Private Attributes

std::map< std::string, Register > fNamed
 

Detailed Description

Definition at line 25 of file RegMap.hpp.

Constructor & Destructor Documentation

◆ RegMap() [1/3]

dunedaq::sspmodules::RegMap::RegMap ( )
inlineprivate

Definition at line 266 of file RegMap.hpp.

266{}

◆ ~RegMap()

dunedaq::sspmodules::RegMap::~RegMap ( )
inlineprivate

Definition at line 267 of file RegMap.hpp.

267{}

◆ RegMap() [2/3]

dunedaq::sspmodules::RegMap::RegMap ( RegMap const & )
privatedelete

◆ RegMap() [3/3]

dunedaq::sspmodules::RegMap::RegMap ( RegMap && )
privatedelete

Member Function Documentation

◆ Get()

dunedaq::sspmodules::RegMap & dunedaq::sspmodules::RegMap::Get ( void )
static

Definition at line 14 of file RegMap.cxx.

15{
16
17 static dunedaq::sspmodules::RegMap* instance = nullptr;
18
19 if (!instance) {
20 instance = new dunedaq::sspmodules::RegMap;
21 // NOTE: All comments about default values, read masks, and write masks are current as of 2/11/2014
22 // clang-format off
23 // Registers in the Zynq ARM Address Address Default Value Read Mask Write Mask Code Name
24 instance->armStatus = 0x00000000; // 0x0000, 0xABCDEF01 0xFFFFFFFF 0x00000000 rregStatus
25 instance->armError = 0x00000004; // 0x0004, 0xEF012345 0xFFFFFFFF 0x00000000 regError
26 instance->armCommand = 0x00000008; // 0x0008, 0x00000000 0xFFFFFFFF 0xFFFFFFFF regCommand
27 instance->armVersion = 0x0000000C; // 0x000C, 0x00000001 0xFFFFFFFF 0x00000000 regVersion
28 instance->armTest[0] = 0x00000010; // 0x0010, 0x12345678 0xFFFFFFFF 0xFFFFFFFF regTest0
29 instance->armTest[1] = 0x00000014; // 0x0014, 0x567890AB 0xFFFFFFFF 0xFFFFFFFF regTest1
30 instance->armTest[2] = 0x00000018; // 0x0018, 0x90ABCDEF 0xFFFFFFFF 0xFFFFFFFF regTest2
31 instance->armTest[3] = 0x0000001C; // 0x001C, 0xCDEF1234 0xFFFFFFFF 0xFFFFFFFF regTest3
32 instance->armRxAddress = 0x00000020; // 0x0020, 0xFFFFFFF0 0xFFFFFFFF 0x00000000 regRxAddress
33 instance->armRxCommand = 0x00000024; // 0x0024, 0xFFFFFFF1 0xFFFFFFFF 0x00000000 regRxCommand
34 instance->armRxSize = 0x00000028; // 0x0028, 0xFFFFFFF2 0xFFFFFFFF 0x00000000 regRxSize
35 instance->armRxStatus = 0x0000002C; // 0x002C, 0xFFFFFFF3 0xFFFFFFFF 0x00000000 regRxStatus
36 instance->armTxAddress = 0x00000030; // 0x0030, 0xFFFFFFF4 0xFFFFFFFF 0x00000000 regTxAddress
37 instance->armTxCommand = 0x00000034; // 0x0034, 0xFFFFFFF5 0xFFFFFFFF 0x00000000 regTxCommand
38 instance->armTxSize = 0x00000038; // 0x0038, 0xFFFFFFF6 0xFFFFFFFF 0x00000000 regTxSize
39 instance->armTxStatus = 0x0000003C; // 0x003C, 0xFFFFFFF7 0xFFFFFFFF 0x00000000 regTxStatus
40 instance->armPackets = 0x00000040; // 0x0040, 0x00000000 0xFFFFFFFF 0x00000000 regPackets
41 instance->armOperMode = 0x00000044; // 0x0044, 0x00000000 0xFFFFFFFF 0x00000000 regOperMode
42 instance->armOptions = 0x00000048; // 0x0048, 0x00000000 0xFFFFFFFF 0x00000000 regOptions
43 instance->armModemStatus = 0x0000004C; // 0x004C, 0x00000000 0xFFFFFFFF 0x00000000 regModemStatus
44 instance->PurgeDDR = 0x00000300; // 0x0300, 0x00000000 0x00000001 0x00000001
45
46 // Registers in the Zynq FPGA Address Address Default Value Read Mask Write Mask VHDL Name
47 instance->zynqTest[0] = 0x40000000; // X"000", X"33333333", X"FFFFFFFF", X"00000000", regin_test_0
48 instance->zynqTest[1] = 0x40000004; // X"004", X"44444444", X"FFFFFFFF", X"00000000", unnamed test register
49 instance->zynqTest[2] = 0x40000008; // X"008", X"55555555", X"FFFFFFFF", X"FFFF0000", unnamed test register
50 instance->zynqTest[3] = 0x4000000C; // X"00C", X"66666666", X"FFFFFFFF", X"0000FFFF", unnamed test register
51 instance->zynqTest[4] = 0x40000010; // X"010", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_test_1
52 instance->zynqTest[5] = 0x40000014; // X"014", X"00000000", X"FFFFFFFF", X"FFFFFFFF", unnamed test register
53 instance->eventDataInterfaceSelect = 0x40000020; // X"020", X"00000000", X"000000F8", X"FFFFFFFF", reg_fake_control
54 instance->fakeNumEvents = 0x40000024; // X"024", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_fake_num_events
55 instance->fakeEventSize = 0x40000028; // X"028", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_fake_event_size
56 instance->fakeBaseline = 0x4000002C; // X"02C", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_fake_baseline
57 instance->fakePeakSum = 0x40000030; // X"030", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_fake_peak_sum
58 instance->fakePrerise = 0x40000034; // X"034", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_fake_prerise
59 instance->timestamp[0] = 0x40000038; // X"038", X"00000000", X"FFFFFFFF", X"00000000", regin_timestamp (low bits)
60 instance->timestamp[1] = 0x4000003C; // X"03C", X"00000000", X"FFFFFFFF", X"00000000", regin_timestamp (high bits);
61 instance->codeErrCounts[0] = 0x40000100; // X"100", X"00000000", X"FFFFFFFF", X"00000000", regin_code_err_counts(0);
62 instance->codeErrCounts[1] = 0x40000104; // X"104", X"00000000", X"FFFFFFFF", X"00000000", regin_code_err_counts(1);
63 instance->codeErrCounts[2] = 0x40000108; // X"108", X"00000000", X"FFFFFFFF", X"00000000", regin_code_err_counts(2);
64 instance->codeErrCounts[3] = 0x4000010C; // X"10C", X"00000000", X"FFFFFFFF", X"00000000", regin_code_err_counts(3);
65 instance->codeErrCounts[4] = 0x40000110; // X"110", X"00000000", X"FFFFFFFF", X"00000000", regin_code_err_counts(4);
66 instance->dispErrCounts[0] = 0x40000120; // X"120", X"00000000", X"FFFFFFFF", X"00000000", regin_disp_err_counts(0);
67 instance->dispErrCounts[1] = 0x40000124; // X"124", X"00000000", X"FFFFFFFF", X"00000000", regin_disp_err_counts(1);
68 instance->dispErrCounts[2] = 0x40000128; // X"128", X"00000000", X"FFFFFFFF", X"00000000", regin_disp_err_counts(2)
69 instance->dispErrCounts[3] = 0x4000012C; // X"12C", X"00000000", X"FFFFFFFF", X"00000000", regin_disp_err_counts(3)
70 instance->dispErrCounts[4] = 0x40000130; // X"130", X"00000000", X"FFFFFFFF", X"00000000", regin_disp_err_counts(4);
71 instance->link_rx_status = 0x40000140; // X"140", X"00000000", X"FFFFFFFF", X"00000000", regin_link_status;
72 instance->eventDataControl = 0x40000144; // X"144", X"0020001F", X"FFFFFFFF", X"0033001F", reg_event_data_control;
73 instance->eventDataPhaseControl = 0x40000148; // X"148", X"00000000", X"00000000", X"00000003", reg_event_data_phase_control;
74 instance->eventDataPhaseStatus = 0x4000014C; // X"14C", X"00000000", X"FFFFFFFF", X"00000000", reg_event_data_phase_status;
75 instance->c2c_master_status = 0x40000150; // X"150", X"00000000", X"FFFFFFFF", X"00000000", regin_c2c_status;
76 instance->c2c_control = 0x40000154; // X"154", X"00000007", X"FFFFFFFF", X"00000007", reg_c2c_control;
77 instance->c2c_master_intr_control = 0x40000158; // X"158", X"00000000", X"FFFFFFFF", X"0000000F", reg_c2c_intr_control;
78 instance->dspStatus = 0x40000160; // X"160", X"00000000", X"FFFFFFFF", X"00000000", regin_dsp_status
79 instance->comm_clock_status = 0x40000170; // X"170", X"00000000", X"FFFFFFFF", X"00000000", regin_clock_status;
80 instance->comm_clock_control = 0x40000174; // X"174", X"00000001", X"FFFFFFFF", X"00000001", reg_clock_control
81 instance->comm_led_config = 0x40000180; // X"180", X"00000000", X"FFFFFFFF", X"00000003", reg_led_config
82 instance->comm_led_input = 0x40000184; // X"184", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_led_input
83 instance->eventDataStatus = 0x40000190; // X"190", X"00000000", X"FFFFFFFF", X"00000000", regin_event_data_status
84 instance->qi_dac_control = 0x40000200; // X"200", X"00000000", X"00000000", X"00000001", reg_qi_dac_control
85 instance->qi_dac_config = 0x40000204; // X"204", X"00008000", X"0003FFFF", X"0003FFFF", reg_qi_dac_config
86
87 instance->bias_control = 0x40000300; // X"300", X"00000000", X"00000000", X"00000001", reg_bias_control
88 instance->bias_status = 0x40000304; // X"304", X"00000000", X"00000FFF", X"00000000", regin_bias_status
89
90 instance->bias_config[0] = 0x40000340; // X"340", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_bias_dac_config(0)
91 instance->bias_config[1] = 0x40000344; // X"344", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_bias_dac_config(1)
92 instance->bias_config[2] = 0x40000348; // X"348", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_bias_dac_config(2)
93 instance->bias_config[3] = 0x4000034C; // X"34C", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_bias_dac_config(3)
94 instance->bias_config[4] = 0x40000350; // X"350", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_bias_dac_config(4)
95 instance->bias_config[5] = 0x40000354; // X"354", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_bias_dac_config(5)
96 instance->bias_config[6] = 0x40000358; // X"358", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_bias_dac_config(6)
97 instance->bias_config[7] = 0x4000035C; // X"35C", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_bias_dac_config(7)
98 instance->bias_config[8] = 0x40000360; // X"360", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_bias_dac_config(8)
99 instance->bias_config[9] = 0x40000364; // X"364", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_bias_dac_config(9)
100 instance->bias_config[10] = 0x40000368; // X"368", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_bias_dac_config(10)
101 instance->bias_config[11] = 0x4000036C; // X"36C", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_bias_dac_config(11)
102
103 instance->bias_readback[0] = 0x40000380; // X"380", X"00000000", X"FFFFFFFF", X"00000000", regin_bias_dac_readback(0)
104 instance->bias_readback[1] = 0x40000384; // X"384", X"00000000", X"FFFFFFFF", X"00000000", regin_bias_dac_readback(1)
105 instance->bias_readback[2] = 0x40000388; // X"388", X"00000000", X"FFFFFFFF", X"00000000", regin_bias_dac_readback(2)
106 instance->bias_readback[3] = 0x4000038C; // X"38C", X"00000000", X"FFFFFFFF", X"00000000", regin_bias_dac_readback(3)
107 instance->bias_readback[4] = 0x40000390; // X"390", X"00000000", X"FFFFFFFF", X"00000000", regin_bias_dac_readback(4)
108 instance->bias_readback[5] = 0x40000394; // X"394", X"00000000", X"FFFFFFFF", X"00000000", regin_bias_dac_readback(5)
109 instance->bias_readback[6] = 0x40000398; // X"398", X"00000000", X"FFFFFFFF", X"00000000", regin_bias_dac_readback(6)
110 instance->bias_readback[7] = 0x4000039C; // X"39C", X"00000000", X"FFFFFFFF", X"00000000", regin_bias_dac_readback(7)
111 instance->bias_readback[8] = 0x400003A0; // X"3A0", X"00000000", X"FFFFFFFF", X"00000000", regin_bias_dac_readback(8)
112 instance->bias_readback[9] = 0x400003A4; // X"3A4", X"00000000", X"FFFFFFFF", X"00000000", regin_bias_dac_readback(9)
113 instance->bias_readback[10] = 0x400003A8; // X"3A8", X"00000000", X"FFFFFFFF", X"00000000", regin_bias_dac_readback(10)
114 instance->bias_readback[11] = 0x400003AC; // X"3AC", X"00000000", X"FFFFFFFF", X"00000000", regin_bias_dac_readback(11)
115
116 instance->vmon_config = 0x40000400; // X"400", X"0012F000", X"00FFFFFF", X"00FFFFFF", reg_vmon_config
117 instance->vmon_select = 0x40000404; // X"404", X"00FFFF00", X"FFFFFFFF", X"FFFFFFFF", reg_vmon_select
118 instance->vmon_gpio = 0x40000408; // X"408", X"00000000", X"0000FFFF", X"0000FFFF", reg_vmon_gpio
119 instance->vmon_config_readback = 0x40000410; // X"410", X"00000000", X"00FFFFFF", X"00000000", regin_vmon_config_readback
120 instance->vmon_select_readback = 0x40000414; // X"414", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_select_readback
121 instance->vmon_gpio_readback = 0x40000418; // X"418", X"00000000", X"0000FFFF", X"00000000", regin_vmon_gpio_readback
122 instance->vmon_id_readback = 0x4000041C; // X"41C", X"00000000", X"000000FF", X"00000000", regin_vmon_id_readback
123 instance->vmon_control = 0x40000420; // X"420", X"00000000", X"00010100", X"00010001", reg_vmon_control & regin_vmon_control
124 instance->vmon_status = 0x40000424; // X"424", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_status
125
126 instance->vmon_bias[0] = 0x40000440; // X"440", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_bias(0)
127 instance->vmon_bias[1] = 0x40000444; // X"444", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_bias(1)
128 instance->vmon_bias[2] = 0x40000448; // X"448", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_bias(2)
129 instance->vmon_bias[3] = 0x4000044C; // X"44C", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_bias(3)
130 instance->vmon_bias[4] = 0x40000450; // X"450", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_bias(4)
131 instance->vmon_bias[5] = 0x40000454; // X"454", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_bias(5)
132 instance->vmon_bias[6] = 0x40000458; // X"458", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_bias(6)
133 instance->vmon_bias[7] = 0x4000045C; // X"45C", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_bias(7)
134 instance->vmon_bias[8] = 0x40000460; // X"460", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_bias(8)
135 instance->vmon_bias[9] = 0x40000464; // X"464", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_bias(9)
136 instance->vmon_bias[10] = 0x40000468; // X"468", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_bias(10)
137 instance->vmon_bias[11] = 0x4000046C; // X"46C", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_bias(11)
138
139 instance->vmon_value[0] = 0x40000480; // X"480", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_value(0)
140 instance->vmon_value[1] = 0x40000484; // X"484", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_value(1)
141 instance->vmon_value[2] = 0x40000488; // X"488", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_value(2)
142 instance->vmon_value[3] = 0x4000048C; // X"48C", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_value(3)
143 instance->vmon_value[4] = 0x40000490; // X"490", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_value(4)
144 instance->vmon_value[5] = 0x40000494; // X"494", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_value(5)
145 instance->vmon_value[6] = 0x40000498; // X"498", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_value(6)
146 instance->vmon_value[7] = 0x4000049C; // X"49C", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_value(7)
147 instance->vmon_value[8] = 0x400004A0; // X"4A0", X"00000000", X"FFFFFFFF", X"00000000", regin_vmon_value(8)
148
149
150 instance->imon_config = 0x40000500; // X"400", X"0012F000", X"00FFFFFF", X"00FFFFFF", reg_imon_config
151 instance->imon_select = 0x40000504; // X"404", X"00FFFF00", X"FFFFFFFF", X"FFFFFFFF", reg_imon_select
152 instance->imon_gpio = 0x40000508; // X"408", X"00000000", X"0000FFFF", X"0000FFFF", reg_imon_gpio
153 instance->imon_config_readback = 0x40000510; // X"410", X"00000000", X"00FFFFFF", X"00000000", regin_imon_config_readback
154 instance->imon_select_readback = 0x40000514; // X"414", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_select_readback
155 instance->imon_gpio_readback = 0x40000518; // X"418", X"00000000", X"0000FFFF", X"00000000", regin_imon_gpio_readback
156 instance->imon_id_readback = 0x4000051C; // X"41C", X"00000000", X"000000FF", X"00000000", regin_imon_id_readback
157 instance->imon_control = 0x40000520; // X"420", X"00000000", X"00010100", X"00010001", reg_imon_control & regin_imon_control
158 instance->imon_status = 0x40000524; // X"424", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_status
159
160 instance->imon_bias[0] = 0x40000540; // X"440", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_bias(0)
161 instance->imon_bias[1] = 0x40000544; // X"444", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_bias(1)
162 instance->imon_bias[2] = 0x40000548; // X"448", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_bias(2)
163 instance->imon_bias[3] = 0x4000054C; // X"44C", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_bias(3)
164 instance->imon_bias[4] = 0x40000550; // X"450", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_bias(4)
165 instance->imon_bias[5] = 0x40000554; // X"454", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_bias(5)
166 instance->imon_bias[6] = 0x40000558; // X"458", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_bias(6)
167 instance->imon_bias[7] = 0x4000055C; // X"45C", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_bias(7)
168 instance->imon_bias[8] = 0x40000560; // X"460", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_bias(8)
169 instance->imon_bias[9] = 0x40000564; // X"464", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_bias(9)
170 instance->imon_bias[10] = 0x40000568; // X"468", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_bias(10)
171 instance->imon_bias[11] = 0x4000056C; // X"46C", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_bias(11)
172
173 instance->imon_value[0] = 0x40000580; // X"480", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_value(0)
174 instance->imon_value[1] = 0x40000584; // X"484", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_value(1)
175 instance->imon_value[2] = 0x40000588; // X"488", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_value(2)
176 instance->imon_value[3] = 0x4000058C; // X"48C", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_value(3)
177 instance->imon_value[4] = 0x40000590; // X"490", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_value(4)
178 instance->imon_value[5] = 0x40000594; // X"494", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_value(5)
179 instance->imon_value[6] = 0x40000598; // X"498", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_value(6)
180 instance->imon_value[7] = 0x4000059C; // X"49C", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_value(7)
181 instance->imon_value[8] = 0x400005A0; // X"4A0", X"00000000", X"FFFFFFFF", X"00000000", regin_imon_value(8)
182
183
184 // Registers in the Artix FPGA Address Default Value Read Mask Write Mask VHDL Name
185 instance->board_id = 0x80000000; // X"000", X"00000000", X"FFFFFFFF", X"00000000", reg_board_id
186 instance->fifo_control = 0x80000004; // X"004", X"00000000", X"0FFFFFFF", X"08000000", reg_fifo_control
187 instance->dp_fpga_fw_build = 0x80000010; // X"004", X"00000000", X"0FFFFFFF", X"08000000", reg_dp_fpga_build
188 instance->calib_build = 0x80000014; // X"004", X"00000000", X"0FFFFFFF", X"08000000", reg_calib_build
189 instance->dp_clock_status = 0x80000020; // X"020", X"00000000", X"FFFFFFFF", X"00000000", reg_dp_clock_status
190 instance->module_id = 0x80000024; // X"024", X"00000000", X"00000FFF", X"00000FFF", reg_module_id
191 instance->c2c_slave_status = 0x80000030; // X"030", X"00000000", X"FFFFFFFF", X"00000000", reg_c2c_status
192 instance->c2c_slave_intr_control = 0x80000034; // X"034", X"00000000", X"FFFFFFFF", X"0000000F", reg_c2c_intr_control
193
194 instance->channel_control[0] = 0x80000040; // X"040", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_channel_control(0)
195 instance->channel_control[1] = 0x80000044; // X"044", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_channel_control(1)
196 instance->channel_control[2] = 0x80000048; // X"048", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_channel_control(2)
197 instance->channel_control[3] = 0x8000004C; // X"04C", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_channel_control(3)
198 instance->channel_control[4] = 0x80000050; // X"050", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_channel_control(4)
199 instance->channel_control[5] = 0x80000054; // X"054", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_channel_control(5)
200 instance->channel_control[6] = 0x80000058; // X"058", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_channel_control(6)
201 instance->channel_control[7] = 0x8000005C; // X"05C", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_channel_control(7)
202 instance->channel_control[8] = 0x80000060; // X"060", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_channel_control(8)
203 instance->channel_control[9] = 0x80000064; // X"064", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_channel_control(9)
204 instance->channel_control[10] = 0x80000068; // X"068", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_channel_control(10)
205 instance->channel_control[11] = 0x8000006C; // X"06C", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_channel_control(11)
206
207 instance->led_threshold[0] = 0x80000080; // X"080", X"00000064", X"00FFFFFF", X"00FFFFFF", reg_led_threshold(0)
208 instance->led_threshold[1] = 0x80000084; // X"084", X"00000064", X"00FFFFFF", X"00FFFFFF", reg_led_threshold(1)
209 instance->led_threshold[2] = 0x80000088; // X"088", X"00000064", X"00FFFFFF", X"00FFFFFF", reg_led_threshold(2)
210 instance->led_threshold[3] = 0x8000008C; // X"08C", X"00000064", X"00FFFFFF", X"00FFFFFF", reg_led_threshold(3)
211 instance->led_threshold[4] = 0x80000090; // X"090", X"00000064", X"00FFFFFF", X"00FFFFFF", reg_led_threshold(4)
212 instance->led_threshold[5] = 0x80000094; // X"094", X"00000064", X"00FFFFFF", X"00FFFFFF", reg_led_threshold(5)
213 instance->led_threshold[6] = 0x80000098; // X"098", X"00000064", X"00FFFFFF", X"00FFFFFF", reg_led_threshold(6)
214 instance->led_threshold[7] = 0x8000009C; // X"09C", X"00000064", X"00FFFFFF", X"00FFFFFF", reg_led_threshold(7)
215 instance->led_threshold[8] = 0x800000A0; // X"0A0", X"00000064", X"00FFFFFF", X"00FFFFFF", reg_led_threshold(8)
216 instance->led_threshold[9] = 0x800000A4; // X"0A4", X"00000064", X"00FFFFFF", X"00FFFFFF", reg_led_threshold(9)
217 instance->led_threshold[10] = 0x800000A8; // X"0A8", X"00000064", X"00FFFFFF", X"00FFFFFF", reg_led_threshold(10)
218 instance->led_threshold[11] = 0x800000AC; // X"0AC", X"00000064", X"00FFFFFF", X"00FFFFFF", reg_led_threshold(11)
219
220 instance->cfd_parameters[0] = 0x800000C0; // X"0C0", X"00001800", X"00001FFF", X"00001FFF", reg_cfd_parameters(0)
221 instance->cfd_parameters[1] = 0x800000C4; // X"0C4", X"00001800", X"00001FFF", X"00001FFF", reg_cfd_parameters(1)
222 instance->cfd_parameters[2] = 0x800000C8; // X"0C8", X"00001800", X"00001FFF", X"00001FFF", reg_cfd_parameters(2)
223 instance->cfd_parameters[3] = 0x800000CC; // X"0CC", X"00001800", X"00001FFF", X"00001FFF", reg_cfd_parameters(3)
224 instance->cfd_parameters[4] = 0x800000D0; // X"0D0", X"00001800", X"00001FFF", X"00001FFF", reg_cfd_parameters(4)
225 instance->cfd_parameters[5] = 0x800000D4; // X"0D4", X"00001800", X"00001FFF", X"00001FFF", reg_cfd_parameters(5)
226 instance->cfd_parameters[6] = 0x800000D8; // X"0D8", X"00001800", X"00001FFF", X"00001FFF", reg_cfd_parameters(6)
227 instance->cfd_parameters[7] = 0x800000DC; // X"0DC", X"00001800", X"00001FFF", X"00001FFF", reg_cfd_parameters(7)
228 instance->cfd_parameters[8] = 0x800000E0; // X"0E0", X"00001800", X"00001FFF", X"00001FFF", reg_cfd_parameters(8)
229 instance->cfd_parameters[9] = 0x800000E4; // X"0E4", X"00001800", X"00001FFF", X"00001FFF", reg_cfd_parameters(9)
230 instance->cfd_parameters[10] = 0x800000E8; // X"0E8", X"00001800", X"00001FFF", X"00001FFF", reg_cfd_parameters(10)
231 instance->cfd_parameters[11] = 0x800000EC; // X"0EC", X"00001800", X"00001FFF", X"00001FFF", reg_cfd_parameters(11)
232
233 instance->readout_pretrigger[0] = 0x80000100; // X"100", X"00000019", X"000007FF", X"000007FF", reg_readout_pretrigger(0)
234 instance->readout_pretrigger[1] = 0x80000104; // X"104", X"00000019", X"000007FF", X"000007FF", reg_readout_pretrigger(1)
235 instance->readout_pretrigger[2] = 0x80000108; // X"108", X"00000019", X"000007FF", X"000007FF", reg_readout_pretrigger(2)
236 instance->readout_pretrigger[3] = 0x8000010C; // X"10C", X"00000019", X"000007FF", X"000007FF", reg_readout_pretrigger(3)
237 instance->readout_pretrigger[4] = 0x80000110; // X"110", X"00000019", X"000007FF", X"000007FF", reg_readout_pretrigger(4)
238 instance->readout_pretrigger[5] = 0x80000114; // X"114", X"00000019", X"000007FF", X"000007FF", reg_readout_pretrigger(5)
239 instance->readout_pretrigger[6] = 0x80000118; // X"118", X"00000019", X"000007FF", X"000007FF", reg_readout_pretrigger(6)
240 instance->readout_pretrigger[7] = 0x8000011C; // X"11C", X"00000019", X"000007FF", X"000007FF", reg_readout_pretrigger(7)
241 instance->readout_pretrigger[8] = 0x80000120; // X"120", X"00000019", X"000007FF", X"000007FF", reg_readout_pretrigger(8)
242 instance->readout_pretrigger[9] = 0x80000124; // X"124", X"00000019", X"000007FF", X"000007FF", reg_readout_pretrigger(9)
243 instance->readout_pretrigger[10] = 0x80000128; // X"128", X"00000019", X"000007FF", X"000007FF", reg_readout_pretrigger(10)
244 instance->readout_pretrigger[11] = 0x8000012C; // X"12C", X"00000019", X"000007FF", X"000007FF", reg_readout_pretrigger(11)
245
246 instance->readout_window[0] = 0x80000140; // X"140", X"000000C8", X"000007FE", X"000007FE", reg_readout_window(0)
247 instance->readout_window[1] = 0x80000144; // X"144", X"000000C8", X"000007FE", X"000007FE", reg_readout_window(1)
248 instance->readout_window[2] = 0x80000148; // X"148", X"000000C8", X"000007FE", X"000007FE", reg_readout_window(2)
249 instance->readout_window[3] = 0x8000014C; // X"14C", X"000000C8", X"000007FE", X"000007FE", reg_readout_window(3)
250 instance->readout_window[4] = 0x80000150; // X"150", X"000000C8", X"000007FE", X"000007FE", reg_readout_window(4)
251 instance->readout_window[5] = 0x80000154; // X"154", X"000000C8", X"000007FE", X"000007FE", reg_readout_window(5)
252 instance->readout_window[6] = 0x80000158; // X"158", X"000000C8", X"000007FE", X"000007FE", reg_readout_window(6)
253 instance->readout_window[7] = 0x8000015C; // X"15C", X"000000C8", X"000007FE", X"000007FE", reg_readout_window(7)
254 instance->readout_window[8] = 0x80000160; // X"160", X"000000C8", X"000007FE", X"000007FE", reg_readout_window(8)
255 instance->readout_window[9] = 0x80000164; // X"164", X"000000C8", X"000007FE", X"000007FE", reg_readout_window(9)
256 instance->readout_window[10] = 0x80000168; // X"168", X"000000C8", X"000007FE", X"000007FE", reg_readout_window(10)
257 instance->readout_window[11] = 0x8000016C; // X"16C", X"000000C8", X"000007FE", X"000007FE", reg_readout_window(11)
258
259 instance->p_window[0] = 0x80000180; // X"180", X"00000000", X"000003FF", X"000003FF", reg_p_window(0)
260 instance->p_window[1] = 0x80000184; // X"184", X"00000000", X"000003FF", X"000003FF", reg_p_window(1)
261 instance->p_window[2] = 0x80000188; // X"188", X"00000000", X"000003FF", X"000003FF", reg_p_window(2)
262 instance->p_window[3] = 0x8000018C; // X"18C", X"00000000", X"000003FF", X"000003FF", reg_p_window(3)
263 instance->p_window[4] = 0x80000190; // X"190", X"00000000", X"000003FF", X"000003FF", reg_p_window(4)
264 instance->p_window[5] = 0x80000194; // X"194", X"00000000", X"000003FF", X"000003FF", reg_p_window(5)
265 instance->p_window[6] = 0x80000198; // X"198", X"00000000", X"000003FF", X"000003FF", reg_p_window(6)
266 instance->p_window[7] = 0x8000019C; // X"19C", X"00000000", X"000003FF", X"000003FF", reg_p_window(7)
267 instance->p_window[8] = 0x800001A0; // X"1A0", X"00000000", X"000003FF", X"000003FF", reg_p_window(8)
268 instance->p_window[9] = 0x800001A4; // X"1A4", X"00000000", X"000003FF", X"000003FF", reg_p_window(9)
269 instance->p_window[10] = 0x800001A8; // X"1A8", X"00000000", X"000003FF", X"000003FF", reg_p_window(10)
270 instance->p_window[11] = 0x800001AC; // X"1AC", X"00000000", X"000003FF", X"000003FF", reg_p_window(11)
271
272 instance->i2_window[0] = 0x800001C0; // X"1C0", X"00000014", X"000003FF", X"000003FF", reg_i2_window(0)
273 instance->i2_window[1] = 0x800001C4; // X"1C4", X"00000014", X"000003FF", X"000003FF", reg_i2_window(1)
274 instance->i2_window[2] = 0x800001C8; // X"1C8", X"00000014", X"000003FF", X"000003FF", reg_i2_window(2)
275 instance->i2_window[3] = 0x800001CC; // X"1CC", X"00000014", X"000003FF", X"000003FF", reg_i2_window(3)
276 instance->i2_window[4] = 0x800001D0; // X"1D0", X"00000014", X"000003FF", X"000003FF", reg_i2_window(4)
277 instance->i2_window[5] = 0x800001D4; // X"1D4", X"00000014", X"000003FF", X"000003FF", reg_i2_window(5)
278 instance->i2_window[6] = 0x800001D8; // X"1D8", X"00000014", X"000003FF", X"000003FF", reg_i2_window(6)
279 instance->i2_window[7] = 0x800001DC; // X"1DC", X"00000014", X"000003FF", X"000003FF", reg_i2_window(7)
280 instance->i2_window[8] = 0x800001E0; // X"1E0", X"00000014", X"000003FF", X"000003FF", reg_i2_window(8)
281 instance->i2_window[9] = 0x800001E4; // X"1E4", X"00000014", X"000003FF", X"000003FF", reg_i2_window(9)
282 instance->i2_window[10] = 0x800001E8; // X"1E8", X"00000014", X"000003FF", X"000003FF", reg_i2_window(10)
283 instance->i2_window[11] = 0x800001EC; // X"1EC", X"00000014", X"000003FF", X"000003FF", reg_i2_window(11)
284
285 instance->m1_window[0] = 0x80000200; // X"200", X"0000000A", X"000003FF", X"000003FF", reg_m1_window(0)
286 instance->m1_window[1] = 0x80000204; // X"204", X"0000000A", X"000003FF", X"000003FF", reg_m1_window(1)
287 instance->m1_window[2] = 0x80000208; // X"208", X"0000000A", X"000003FF", X"000003FF", reg_m1_window(2)
288 instance->m1_window[3] = 0x8000020C; // X"20C", X"0000000A", X"000003FF", X"000003FF", reg_m1_window(3)
289 instance->m1_window[4] = 0x80000210; // X"210", X"0000000A", X"000003FF", X"000003FF", reg_m1_window(4)
290 instance->m1_window[5] = 0x80000214; // X"214", X"0000000A", X"000003FF", X"000003FF", reg_m1_window(5)
291 instance->m1_window[6] = 0x80000218; // X"218", X"0000000A", X"000003FF", X"000003FF", reg_m1_window(6)
292 instance->m1_window[7] = 0x8000021C; // X"21C", X"0000000A", X"000003FF", X"000003FF", reg_m1_window(7)
293 instance->m1_window[8] = 0x80000220; // X"220", X"0000000A", X"000003FF", X"000003FF", reg_m1_window(8)
294 instance->m1_window[9] = 0x80000224; // X"224", X"0000000A", X"000003FF", X"000003FF", reg_m1_window(9)
295 instance->m1_window[10] = 0x80000228; // X"228", X"0000000A", X"000003FF", X"000003FF", reg_m1_window(10)
296 instance->m1_window[11] = 0x8000022C; // X"22C", X"0000000A", X"000003FF", X"000003FF", reg_m1_window(11)
297
298 instance->m2_window[0] = 0x80000240; // X"240", X"00000014", X"0000007F", X"0000007F", reg_m2_window(0)
299 instance->m2_window[1] = 0x80000244; // X"244", X"00000014", X"0000007F", X"0000007F", reg_m2_window(1)
300 instance->m2_window[2] = 0x80000248; // X"248", X"00000014", X"0000007F", X"0000007F", reg_m2_window(2)
301 instance->m2_window[3] = 0x8000024C; // X"24C", X"00000014", X"0000007F", X"0000007F", reg_m2_window(3)
302 instance->m2_window[4] = 0x80000250; // X"250", X"00000014", X"0000007F", X"0000007F", reg_m2_window(4)
303 instance->m2_window[5] = 0x80000254; // X"254", X"00000014", X"0000007F", X"0000007F", reg_m2_window(5)
304 instance->m2_window[6] = 0x80000258; // X"258", X"00000014", X"0000007F", X"0000007F", reg_m2_window(6)
305 instance->m2_window[7] = 0x8000025C; // X"25C", X"00000014", X"0000007F", X"0000007F", reg_m2_window(7)
306 instance->m2_window[8] = 0x80000260; // X"260", X"00000014", X"0000007F", X"0000007F", reg_m2_window(8)
307 instance->m2_window[9] = 0x80000264; // X"264", X"00000014", X"0000007F", X"0000007F", reg_m2_window(9)
308 instance->m2_window[10] = 0x80000268; // X"268", X"00000014", X"0000007F", X"0000007F", reg_m2_window(10)
309 instance->m2_window[11] = 0x8000026C; // X"26C", X"00000014", X"0000007F", X"0000007F", reg_m2_window(11)
310
311 instance->d_window[0] = 0x80000280; // X"280", X"00000014", X"0000007F", X"0000007F", reg_d_window(0)
312 instance->d_window[1] = 0x80000284; // X"284", X"00000014", X"0000007F", X"0000007F", reg_d_window(1)
313 instance->d_window[2] = 0x80000288; // X"288", X"00000014", X"0000007F", X"0000007F", reg_d_window(2)
314 instance->d_window[3] = 0x8000028C; // X"28C", X"00000014", X"0000007F", X"0000007F", reg_d_window(3)
315 instance->d_window[4] = 0x80000290; // X"290", X"00000014", X"0000007F", X"0000007F", reg_d_window(4)
316 instance->d_window[5] = 0x80000294; // X"294", X"00000014", X"0000007F", X"0000007F", reg_d_window(5)
317 instance->d_window[6] = 0x80000298; // X"298", X"00000014", X"0000007F", X"0000007F", reg_d_window(6)
318 instance->d_window[7] = 0x8000029C; // X"29C", X"00000014", X"0000007F", X"0000007F", reg_d_window(7)
319 instance->d_window[8] = 0x800002A0; // X"2A0", X"00000014", X"0000007F", X"0000007F", reg_d_window(8)
320 instance->d_window[9] = 0x800002A4; // X"2A4", X"00000014", X"0000007F", X"0000007F", reg_d_window(9)
321 instance->d_window[10] = 0x800002A8; // X"2A8", X"00000014", X"0000007F", X"0000007F", reg_d_window(10)
322 instance->d_window[11] = 0x800002AC; // X"2AC", X"00000014", X"0000007F", X"0000007F", reg_d_window(11)
323
324 instance->i1_window[0] = 0x800002C0; // X"2C0", X"00000010", X"000003FF", X"000003FF", reg_i1_window(0)
325 instance->i1_window[1] = 0x800002C4; // X"2C4", X"00000010", X"000003FF", X"000003FF", reg_i1_window(1)
326 instance->i1_window[2] = 0x800002C8; // X"2C8", X"00000010", X"000003FF", X"000003FF", reg_i1_window(2)
327 instance->i1_window[3] = 0x800002CC; // X"2CC", X"00000010", X"000003FF", X"000003FF", reg_i1_window(3)
328 instance->i1_window[4] = 0x800002D0; // X"2D0", X"00000010", X"000003FF", X"000003FF", reg_i1_window(4)
329 instance->i1_window[5] = 0x800002D4; // X"2D4", X"00000010", X"000003FF", X"000003FF", reg_i1_window(5)
330 instance->i1_window[6] = 0x800002D8; // X"2D8", X"00000010", X"000003FF", X"000003FF", reg_i1_window(6)
331 instance->i1_window[7] = 0x800002DC; // X"2DC", X"00000010", X"000003FF", X"000003FF", reg_i1_window(7)
332 instance->i1_window[8] = 0x800002E0; // X"2E0", X"00000010", X"000003FF", X"000003FF", reg_i1_window(8)
333 instance->i1_window[9] = 0x800002E4; // X"2E4", X"00000010", X"000003FF", X"000003FF", reg_i1_window(9)
334 instance->i1_window[10] = 0x800002E8; // X"2E8", X"00000010", X"000003FF", X"000003FF", reg_i1_window(10)
335 instance->i1_window[11] = 0x800002EC; // X"2EC", X"00000010", X"000003FF", X"000003FF", reg_i1_window(11)
336
337 instance->disc_width[0] = 0x80000300; // X"300", X"00000000", X"0000FFFF", X"0000FFFF", reg_disc_width(0)
338 instance->disc_width[1] = 0x80000304; // X"304", X"00000000", X"0000FFFF", X"0000FFFF", reg_disc_width(1)
339 instance->disc_width[2] = 0x80000308; // X"308", X"00000000", X"0000FFFF", X"0000FFFF", reg_disc_width(2)
340 instance->disc_width[3] = 0x8000030C; // X"30C", X"00000000", X"0000FFFF", X"0000FFFF", reg_disc_width(3)
341 instance->disc_width[4] = 0x80000310; // X"310", X"00000000", X"0000FFFF", X"0000FFFF", reg_disc_width(4)
342 instance->disc_width[5] = 0x80000314; // X"314", X"00000000", X"0000FFFF", X"0000FFFF", reg_disc_width(5)
343 instance->disc_width[6] = 0x80000318; // X"318", X"00000000", X"0000FFFF", X"0000FFFF", reg_disc_width(6)
344 instance->disc_width[7] = 0x8000031C; // X"31C", X"00000000", X"0000FFFF", X"0000FFFF", reg_disc_width(7)
345 instance->disc_width[8] = 0x80000320; // X"320", X"00000000", X"0000FFFF", X"0000FFFF", reg_disc_width(8)
346 instance->disc_width[9] = 0x80000324; // X"324", X"00000000", X"0000FFFF", X"0000FFFF", reg_disc_width(9)
347 instance->disc_width[10] = 0x80000328; // X"328", X"00000000", X"0000FFFF", X"0000FFFF", reg_disc_width(10)
348 instance->disc_width[11] = 0x8000032C; // X"32C", X"00000000", X"0000FFFF", X"0000FFFF", reg_disc_width(11)
349
350 instance->baseline_start[0] = 0x80000340; // X"340", X"00002000", X"00003FFF", X"00003FFF", reg_baseline_start(0)
351 instance->baseline_start[1] = 0x80000344; // X"344", X"00002000", X"00003FFF", X"00003FFF", reg_baseline_start(1)
352 instance->baseline_start[2] = 0x80000348; // X"348", X"00002000", X"00003FFF", X"00003FFF", reg_baseline_start(2)
353 instance->baseline_start[3] = 0x8000034C; // X"34C", X"00002000", X"00003FFF", X"00003FFF", reg_baseline_start(3)
354 instance->baseline_start[4] = 0x80000350; // X"350", X"00002000", X"00003FFF", X"00003FFF", reg_baseline_start(4)
355 instance->baseline_start[5] = 0x80000354; // X"354", X"00002000", X"00003FFF", X"00003FFF", reg_baseline_start(5)
356 instance->baseline_start[6] = 0x80000358; // X"358", X"00002000", X"00003FFF", X"00003FFF", reg_baseline_start(6)
357 instance->baseline_start[7] = 0x8000035C; // X"35C", X"00002000", X"00003FFF", X"00003FFF", reg_baseline_start(7)
358 instance->baseline_start[8] = 0x80000360; // X"360", X"00002000", X"00003FFF", X"00003FFF", reg_baseline_start(8)
359 instance->baseline_start[9] = 0x80000364; // X"364", X"00002000", X"00003FFF", X"00003FFF", reg_baseline_start(9)
360 instance->baseline_start[10] = 0x80000368; // X"368", X"00002000", X"00003FFF", X"00003FFF", reg_baseline_start(10)
361 instance->baseline_start[11] = 0x8000036C; // X"36C", X"00002000", X"00003FFF", X"00003FFF", reg_baseline_start(11)
362 instance->c_window[0] = 0x80000380; // X"340", X"00002000", X"00003FFF", X"00003FFF", reg_c_window(0)
363 instance->c_window[1] = 0x80000384; // X"344", X"00002000", X"00003FFF", X"00003FFF", reg_c_window(1)
364 instance->c_window[2] = 0x80000388; // X"348", X"00002000", X"00003FFF", X"00003FFF", reg_c_window(2)
365 instance->c_window[3] = 0x8000038C; // X"34C", X"00002000", X"00003FFF", X"00003FFF", reg_c_window(3)
366 instance->c_window[4] = 0x80000390; // X"350", X"00002000", X"00003FFF", X"00003FFF", reg_c_window(4)
367 instance->c_window[5] = 0x80000394; // X"354", X"00002000", X"00003FFF", X"00003FFF", reg_c_window(5)
368 instance->c_window[6] = 0x80000398; // X"358", X"00002000", X"00003FFF", X"00003FFF", reg_c_window(6)
369 instance->c_window[7] = 0x8000039C; // X"35C", X"00002000", X"00003FFF", X"00003FFF", reg_c_window(7)
370 instance->c_window[8] = 0x800003A0; // X"360", X"00002000", X"00003FFF", X"00003FFF", reg_c_window(8)
371 instance->c_window[9] = 0x800003A4; // X"364", X"00002000", X"00003FFF", X"00003FFF", reg_c_window(9)
372 instance->c_window[10] = 0x800003A8; // X"368", X"00002000", X"00003FFF", X"00003FFF", reg_c_window(10)
373 instance->c_window[11] = 0x800003AC; // X"36C", X"00002000", X"00003FFF", X"00003FFF", reg_c_window(11)
374
375 instance->trigger_input_delay = 0x80000400; // X"400", X"00000010", X"0000FFFF", X"0000FFFF", reg_trigger_input_delay
376 instance->gpio_output_width = 0x80000404; // X"404", X"0000000F", X"0000FFFF", X"0000FFFF", reg_gpio_output_width
377 instance->front_panel_config = 0x80000408; // X"408", X"00000111", X"00730333", X"00730333", reg_misc_config
378 instance->channel_pulsed_control = 0x8000040C; // X"40C", X"00000000", X"00000000", X"FFFFFFFF", reg_channel_pulsed_control
379 instance->dsp_led_config = 0x80000410; // X"410", X"00000000", X"FFFFFFFF", X"00000003", reg_led_config
380 instance->dsp_led_input = 0x80000414; // X"414", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_led_input
381 instance->baseline_delay = 0x80000418; // X"418", X"00000019", X"000000FF", X"000000FF", reg_baseline_delay
382 instance->diag_channel_input = 0x8000041C; // X"41C", X"00000000", X"FFFFFFFF", X"FFFFFFFF", reg_diag_channel_input
383 instance->event_data_control = 0x80000424; // X"424", X"00000001", X"00020001", X"00020001", reg_event_data_control
384 instance->adc_config = 0x80000428; // X"428", X"00010000", X"FFFFFFFF", X"FFFFFFFF", reg_adc_config
385 instance->adc_config_load = 0x8000042C; // X"42C", X"00000000", X"00000000", X"00000001", reg_adc_config_load
386 instance->qi_config = 0x80000430; // X"430", X"0FFF1700", X"0FFF1F11", X"0FFF1F11", reg_qi_config
387 instance->qi_delay = 0x80000434; // X"434", X"00000000", X"0000007F", X"0000007F", reg_qi_delay
388 instance->qi_pulse_width = 0x80000438; // X"438", X"00000000", X"0000FFFF", X"0000FFFF", reg_qi_pulse_width
389 instance->qi_pulsed = 0x8000043C; // X"43C", X"00000000", X"00000000", X"00030001", reg_qi_pulsed
390 instance->external_gate_width = 0x80000440; // X"440", X"00008000", X"0000FFFF", X"0000FFFF", reg_external_gate_width
391 instance->pdts_cmd_control[0] = 0x80000460; // X"440", X"00008000", X"0000FFFF", X"0000FFFF", reg_pdts_cmd_control(0)
392 instance->pdts_cmd_control[1] = 0x80000464; // X"440", X"00008000", X"0000FFFF", X"0000FFFF", reg_pdts_cmd_control(1)
393 instance->pdts_cmd_control[2] = 0x80000468; // X"440", X"00008000", X"0000FFFF", X"0000FFFF", reg_pdts_cmd_control(2)
394 instance->lat_timestamp_lsb = 0x80000484; // X"484", X"00000000", X"FFFFFFFF", X"00000000", reg_lat_timestamp (lsb)
395 instance->lat_timestamp_msb = 0x80000488; // X"488", X"00000000", X"0000FFFF", X"00000000", reg_lat_timestamp (msb)
396 instance->live_timestamp_lsb = 0x8000048C; // X"48C", X"00000000", X"FFFFFFFF", X"00000000", reg_live_timestamp (lsb)
397 instance->live_timestamp_msb = 0x80000490; // X"490", X"00000000", X"0000FFFF", X"00000000", reg_live_timestamp (msb)
398 instance->sync_period = 0x80000494; // X"494", X"00000000", X"FFFFFFFF", X"00000000", reg_last_sync_reset_count
399 instance->sync_delay = 0x80000498; // X"498", X"00000000", X"FFFFFFFF", X"00000000", reg_external_timestamp (lsb)
400 instance->sync_count = 0x8000049C; // X"49C", X"00000000", X"FFFFFFFF", X"00000000", reg_external_timestamp (msb)
401 instance->pdts_control = 0x800004C0;
402 instance->pdts_status = 0x800004C4;
403 instance->pdts_ts_preset[0] = 0x800004C8;
404 instance->pdts_ts_preset[1] = 0x800004CC;
405 instance->master_logic_control = 0x80000500; // X"500", X"00000000", X"FFFFFFFF", X"00000073", reg_master_logic_status
406 instance->master_logic_status = 0x80000504; // X"504", X"00000000", X"00000003", X"00000003", reg_trigger_config
407 instance->overflow_status = 0x80000508; // X"508", X"00000000", X"FFFFFFFF", X"00000000", reg_overflow_status
408 instance->phase_value = 0x8000050C; // X"50C", X"00000000", X"FFFFFFFF", X"00000000", reg_phase_value
409 instance->link_tx_status = 0x80000510; // X"510", X"00000000", X"FFFFFFFF", X"00000000", reg_link_status
410
411 instance->dsp_clock_control = 0x80000520; // X"520", X"00000000", X"00000713", X"00000713", reg_dsp_clock_control
412 instance->dsp_clock_phase_control = 0x80000524; // X"524", X"00000000", X"00000000", X"00000007", reg_dsp_clock_phase_control
413
414 instance->code_revision = 0x80000600; // X"600", X"00000000", X"FFFFFFFF", X"00000000", reg_code_revision
415 instance->code_date = 0x80000604; // X"604", X"00000000", X"FFFFFFFF", X"00000000", reg_code_date
416
417 instance->dropped_event_count[0] = 0x80000700; // X"700", X"00000000", X"FFFFFFFF", X"00000000", reg_dropped_event_count(0)
418 instance->dropped_event_count[1] = 0x80000704; // X"704", X"00000000", X"FFFFFFFF", X"00000000", reg_dropped_event_count(1)
419 instance->dropped_event_count[2] = 0x80000708; // X"708", X"00000000", X"FFFFFFFF", X"00000000", reg_dropped_event_count(2)
420 instance->dropped_event_count[3] = 0x8000070C; // X"70C", X"00000000", X"FFFFFFFF", X"00000000", reg_dropped_event_count(3)
421 instance->dropped_event_count[4] = 0x80000710; // X"710", X"00000000", X"FFFFFFFF", X"00000000", reg_dropped_event_count(4)
422 instance->dropped_event_count[5] = 0x80000714; // X"714", X"00000000", X"FFFFFFFF", X"00000000", reg_dropped_event_count(5)
423 instance->dropped_event_count[6] = 0x80000718; // X"718", X"00000000", X"FFFFFFFF", X"00000000", reg_dropped_event_count(6)
424 instance->dropped_event_count[7] = 0x8000071C; // X"71C", X"00000000", X"FFFFFFFF", X"00000000", reg_dropped_event_count(7)
425 instance->dropped_event_count[8] = 0x80000720; // X"720", X"00000000", X"FFFFFFFF", X"00000000", reg_dropped_event_count(8)
426 instance->dropped_event_count[9] = 0x80000724; // X"724", X"00000000", X"FFFFFFFF", X"00000000", reg_dropped_event_count(9)
427 instance->dropped_event_count[10] = 0x80000728; // X"728", X"00000000", X"FFFFFFFF", X"00000000", reg_dropped_event_count(10)
428 instance->dropped_event_count[11] = 0x8000072C; // X"72C", X"00000000", X"FFFFFFFF", X"00000000", reg_dropped_event_count(11)
429
430 instance->accepted_event_count[0] = 0x80000740; // X"740", X"00000000", X"FFFFFFFF", X"00000000", reg_accepted_event_count(0)
431 instance->accepted_event_count[1] = 0x80000744; // X"744", X"00000000", X"FFFFFFFF", X"00000000", reg_accepted_event_count(1)
432 instance->accepted_event_count[2] = 0x80000748; // X"748", X"00000000", X"FFFFFFFF", X"00000000", reg_accepted_event_count(2)
433 instance->accepted_event_count[3] = 0x8000074C; // X"74C", X"00000000", X"FFFFFFFF", X"00000000", reg_accepted_event_count(3)
434 instance->accepted_event_count[4] = 0x80000750; // X"750", X"00000000", X"FFFFFFFF", X"00000000", reg_accepted_event_count(4)
435 instance->accepted_event_count[5] = 0x80000754; // X"754", X"00000000", X"FFFFFFFF", X"00000000", reg_accepted_event_count(5)
436 instance->accepted_event_count[6] = 0x80000758; // X"758", X"00000000", X"FFFFFFFF", X"00000000", reg_accepted_event_count(6)
437 instance->accepted_event_count[7] = 0x8000075C; // X"75C", X"00000000", X"FFFFFFFF", X"00000000", reg_accepted_event_count(7)
438 instance->accepted_event_count[8] = 0x80000760; // X"760", X"00000000", X"FFFFFFFF", X"00000000", reg_accepted_event_count(8)
439 instance->accepted_event_count[9] = 0x80000764; // X"764", X"00000000", X"FFFFFFFF", X"00000000", reg_accepted_event_count(9)
440 instance->accepted_event_count[10] = 0x80000768; // X"768", X"00000000", X"FFFFFFFF", X"00000000", reg_accepted_event_count(10)
441 instance->accepted_event_count[11] = 0x8000076C; // X"76C", X"00000000", X"FFFFFFFF", X"00000000", reg_accepted_event_count(11)
442
443 instance->ahit_count[0] = 0x80000780; // X"780", X"00000000", X"FFFFFFFF", X"00000000", reg_ahit_count(0)
444 instance->ahit_count[1] = 0x80000784; // X"784", X"00000000", X"FFFFFFFF", X"00000000", reg_ahit_count(1)
445 instance->ahit_count[2] = 0x80000788; // X"788", X"00000000", X"FFFFFFFF", X"00000000", reg_ahit_count(2)
446 instance->ahit_count[3] = 0x8000078C; // X"78C", X"00000000", X"FFFFFFFF", X"00000000", reg_ahit_count(3)
447 instance->ahit_count[4] = 0x80000790; // X"790", X"00000000", X"FFFFFFFF", X"00000000", reg_ahit_count(4)
448 instance->ahit_count[5] = 0x80000794; // X"794", X"00000000", X"FFFFFFFF", X"00000000", reg_ahit_count(5)
449 instance->ahit_count[6] = 0x80000798; // X"798", X"00000000", X"FFFFFFFF", X"00000000", reg_ahit_count(6)
450 instance->ahit_count[7] = 0x8000079C; // X"79C", X"00000000", X"FFFFFFFF", X"00000000", reg_ahit_count(7)
451 instance->ahit_count[8] = 0x800007A0; // X"7A0", X"00000000", X"FFFFFFFF", X"00000000", reg_ahit_count(8)
452 instance->ahit_count[9] = 0x800007A4; // X"7A4", X"00000000", X"FFFFFFFF", X"00000000", reg_ahit_count(9)
453 instance->ahit_count[10] = 0x800007A8; // X"7A8", X"00000000", X"FFFFFFFF", X"00000000", reg_ahit_count(10)
454 instance->ahit_count[11] = 0x800007AC; // X"7AC", X"00000000", X"FFFFFFFF", X"00000000", reg_ahit_count(11)
455
456 instance->disc_count[0] = 0x800007C0; // X"7C0", X"00000000", X"FFFFFFFF", X"00000000", reg_disc_count(0)
457 instance->disc_count[1] = 0x800007C4; // X"7C4", X"00000000", X"FFFFFFFF", X"00000000", reg_disc_count(1)
458 instance->disc_count[2] = 0x800007C8; // X"7C8", X"00000000", X"FFFFFFFF", X"00000000", reg_disc_count(2)
459 instance->disc_count[3] = 0x800007CC; // X"7CC", X"00000000", X"FFFFFFFF", X"00000000", reg_disc_count(3)
460 instance->disc_count[4] = 0x800007D0; // X"7D0", X"00000000", X"FFFFFFFF", X"00000000", reg_disc_count(4)
461 instance->disc_count[5] = 0x800007D4; // X"7D4", X"00000000", X"FFFFFFFF", X"00000000", reg_disc_count(5)
462 instance->disc_count[6] = 0x800007D8; // X"7D8", X"00000000", X"FFFFFFFF", X"00000000", reg_disc_count(6)
463 instance->disc_count[7] = 0x800007DC; // X"7DC", X"00000000", X"FFFFFFFF", X"00000000", reg_disc_count(7)
464 instance->disc_count[8] = 0x800007E0; // X"7E0", X"00000000", X"FFFFFFFF", X"00000000", reg_disc_count(8)
465 instance->disc_count[9] = 0x800007E4; // X"7E4", X"00000000", X"FFFFFFFF", X"00000000", reg_disc_count(9)
466 instance->disc_count[10] = 0x800007E8; // X"7E8", X"00000000", X"FFFFFFFF", X"00000000", reg_disc_count(10)
467 instance->disc_count[11] = 0x800007EC; // X"7EC", X"00000000", X"FFFFFFFF", X"00000000", reg_disc_count(11)
468
469 instance->idelay_count[0] = 0x80000800; // X"800", X"00000000", X"FFFFFFFF", X"00000000", reg_idelay_count(0)
470 instance->idelay_count[1] = 0x80000804; // X"804", X"00000000", X"FFFFFFFF", X"00000000", reg_idelay_count(1)
471 instance->idelay_count[2] = 0x80000808; // X"808", X"00000000", X"FFFFFFFF", X"00000000", reg_idelay_count(2)
472 instance->idelay_count[3] = 0x8000080C; // X"80C", X"00000000", X"FFFFFFFF", X"00000000", reg_idelay_count(3)
473 instance->idelay_count[4] = 0x80000810; // X"810", X"00000000", X"FFFFFFFF", X"00000000", reg_idelay_count(4)
474 instance->idelay_count[5] = 0x80000814; // X"814", X"00000000", X"FFFFFFFF", X"00000000", reg_idelay_count(5)
475 instance->idelay_count[6] = 0x80000818; // X"818", X"00000000", X"FFFFFFFF", X"00000000", reg_idelay_count(6)
476 instance->idelay_count[7] = 0x8000081C; // X"81C", X"00000000", X"FFFFFFFF", X"00000000", reg_idelay_count(7)
477 instance->idelay_count[8] = 0x80000820; // X"820", X"00000000", X"FFFFFFFF", X"00000000", reg_idelay_count(8)
478 instance->idelay_count[9] = 0x80000824; // X"824", X"00000000", X"FFFFFFFF", X"00000000", reg_idelay_count(9)
479 instance->idelay_count[10] = 0x80000828; // X"828", X"00000000", X"FFFFFFFF", X"00000000", reg_idelay_count(10)
480 instance->idelay_count[11] = 0x8000082C; // X"82C", X"00000000", X"FFFFFFFF", X"00000000", reg_idelay_count(11)
481
482 instance->adc_data_monitor[0] = 0x80000840; // X"840", X"00000000", X"0000FFFF", X"00000000", reg_adc_data_monitor(0)
483 instance->adc_data_monitor[1] = 0x80000844; // X"844", X"00000000", X"0000FFFF", X"00000000", reg_adc_data_monitor(1)
484 instance->adc_data_monitor[2] = 0x80000848; // X"848", X"00000000", X"0000FFFF", X"00000000", reg_adc_data_monitor(2)
485 instance->adc_data_monitor[3] = 0x8000084C; // X"84C", X"00000000", X"0000FFFF", X"00000000", reg_adc_data_monitor(3)
486 instance->adc_data_monitor[4] = 0x80000850; // X"850", X"00000000", X"0000FFFF", X"00000000", reg_adc_data_monitor(4)
487 instance->adc_data_monitor[5] = 0x80000854; // X"854", X"00000000", X"0000FFFF", X"00000000", reg_adc_data_monitor(5)
488 instance->adc_data_monitor[6] = 0x80000858; // X"858", X"00000000", X"0000FFFF", X"00000000", reg_adc_data_monitor(6)
489 instance->adc_data_monitor[7] = 0x8000085C; // X"85C", X"00000000", X"0000FFFF", X"00000000", reg_adc_data_monitor(7)
490 instance->adc_data_monitor[8] = 0x80000860; // X"860", X"00000000", X"0000FFFF", X"00000000", reg_adc_data_monitor(8)
491 instance->adc_data_monitor[9] = 0x80000864; // X"864", X"00000000", X"0000FFFF", X"00000000", reg_adc_data_monitor(9)
492 instance->adc_data_monitor[10] = 0x80000868; // X"868", X"00000000", X"0000FFFF", X"00000000", reg_adc_data_monitor(10)
493 instance->adc_data_monitor[11] = 0x8000086C; // X"86C", X"00000000", X"0000FFFF", X"00000000", reg_adc_data_monitor(11)
494
495 instance->adc_status[0] = 0x80000880; // X"880", X"00000000", X"FFFFFFFF", X"00000000", reg_adc_status(0)
496 instance->adc_status[1] = 0x80000884; // X"884", X"00000000", X"FFFFFFFF", X"00000000", reg_adc_status(1)
497 instance->adc_status[2] = 0x80000888; // X"888", X"00000000", X"FFFFFFFF", X"00000000", reg_adc_status(2)
498 instance->adc_status[3] = 0x8000088C; // X"88C", X"00000000", X"FFFFFFFF", X"00000000", reg_adc_status(3)
499 instance->adc_status[4] = 0x80000890; // X"890", X"00000000", X"FFFFFFFF", X"00000000", reg_adc_status(4)
500 instance->adc_status[5] = 0x80000894; // X"894", X"00000000", X"FFFFFFFF", X"00000000", reg_adc_status(5)
501 instance->adc_status[6] = 0x80000898; // X"898", X"00000000", X"FFFFFFFF", X"00000000", reg_adc_status(6)
502 instance->adc_status[7] = 0x8000089C; // X"89C", X"00000000", X"FFFFFFFF", X"00000000", reg_adc_status(7)
503 instance->adc_status[8] = 0x800008A0; // X"8A0", X"00000000", X"FFFFFFFF", X"00000000", reg_adc_status(8)
504 instance->adc_status[9] = 0x800008A4; // X"8A4", X"00000000", X"FFFFFFFF", X"00000000", reg_adc_status(9)
505 instance->adc_status[10] = 0x800008A8; // X"8A8", X"00000000", X"FFFFFFFF", X"00000000", reg_adc_status(10)
506 instance->adc_status[11] = 0x800008AC; // X"8AC", X"00000000", X"FFFFFFFF", X"00000000", reg_adc_status(11)
507
508// Name Address Read Mask Write Mask Size
509
510 instance->fNamed["armStatus"] =Register( 0x00000000, 0xFFFFFFFF, 0x00000000, 1 );
511 instance->fNamed["armError"] =Register( 0x00000004, 0xFFFFFFFF, 0x00000000, 1 );
512 instance->fNamed["armCommand"] =Register( 0x00000008, 0xFFFFFFFF, 0xFFFFFFFF, 1 );
513 instance->fNamed["armVersion"] =Register( 0x0000000C, 0xFFFFFFFF, 0x00000000, 1 );
514 instance->fNamed["armTest"] =Register( 0x00000010, 0xFFFFFFFF, 0xFFFFFFFF, 4 );
515 instance->fNamed["armRxAddress"] =Register( 0x00000020, 0xFFFFFFFF, 0x00000000, 1 );
516 instance->fNamed["armRxCommand"] =Register( 0x00000024, 0xFFFFFFFF, 0x00000000, 1 );
517 instance->fNamed["armRxSize"] =Register( 0x00000028, 0xFFFFFFFF, 0x00000000, 1 );
518 instance->fNamed["armRxStatus"] =Register( 0x0000002C, 0xFFFFFFFF, 0x00000000, 1 );
519 instance->fNamed["armTxAddress"] =Register( 0x00000030, 0xFFFFFFFF, 0x00000000, 1 );
520 instance->fNamed["armTxCommand"] =Register( 0x00000034, 0xFFFFFFFF, 0x00000000, 1 );
521 instance->fNamed["armTxSize"] =Register( 0x00000038, 0xFFFFFFFF, 0x00000000, 1 );
522 instance->fNamed["armTxStatus"] =Register( 0x0000003C, 0xFFFFFFFF, 0x00000000, 1 );
523 instance->fNamed["armPackets"] =Register( 0x00000040, 0xFFFFFFFF, 0x00000000, 1 );
524 instance->fNamed["armOperMode"] =Register( 0x00000044, 0xFFFFFFFF, 0x00000000, 1 );
525 instance->fNamed["armOptions"] =Register( 0x00000048, 0xFFFFFFFF, 0x00000000, 1 );
526 instance->fNamed["armModemStatus"] =Register( 0x0000004C, 0xFFFFFFFF, 0x00000000, 1 );
527 instance->fNamed["PurgeDDR"] =Register( 0x00000300, 0x00000001, 0x00000001, 1 );
528 instance->fNamed["zynqTest"] =Register( 0x40000000, 0xFFFFFFFF, 0x00000000, 6 );
529 instance->fNamed["eventDataInterfaceSelect"]=Register( 0x40000020, 0xFFFFFFFF, 0x00000001, 1 );
530 instance->fNamed["fakeNumEvents"] =Register( 0x40000024, 0xFFFFFFFF, 0xFFFFFFFF, 1 );
531 instance->fNamed["fakeEventSize"] =Register( 0x40000028, 0xFFFFFFFF, 0xFFFFFFFF, 1 );
532 instance->fNamed["fakeBaseline"] =Register( 0x4000002C, 0xFFFFFFFF, 0xFFFFFFFF, 1 );
533 instance->fNamed["fakePeakSum"] =Register( 0x40000030, 0xFFFFFFFF, 0xFFFFFFFF, 1 );
534 instance->fNamed["fakePrerise"] =Register( 0x40000034, 0xFFFFFFFF, 0xFFFFFFFF, 1 );
535 instance->fNamed["timestamp"] =Register( 0x40000038, 0xFFFFFFFF, 0x00000000, 2 );
536 instance->fNamed["codeErrCounts"] =Register( 0x40000100, 0xFFFFFFFF, 0x00000000, 5 );
537 instance->fNamed["dispErrCounts"] =Register( 0x40000120, 0xFFFFFFFF, 0x00000000, 5 );
538 instance->fNamed["link_rx_status"] =Register( 0x40000140, 0xFFFFFFFF, 0x00000000, 1 );
539 instance->fNamed["eventDataControl"] =Register( 0x40000144, 0xFFFFFFFF, 0x0033001F, 1 );
540 instance->fNamed["eventDataPhaseControl"] =Register( 0x40000148, 0x00000000, 0x00000003, 1 );
541 instance->fNamed["eventDataPhaseStatus"] =Register( 0x4000014C, 0xFFFFFFFF, 0x00000000, 1 );
542 instance->fNamed["c2c_master_status"] =Register( 0x40000150, 0xFFFFFFFF, 0x00000000, 1 );
543 instance->fNamed["c2c_control"] =Register( 0x40000154, 0xFFFFFFFF, 0x00000007, 1 );
544 instance->fNamed["c2c_master_intr_control"] =Register( 0x40000158, 0xFFFFFFFF, 0x0000000F, 1 );
545 instance->fNamed["dspStatus"] =Register( 0x40000160, 0xFFFFFFFF, 0x00000000, 1 );
546 instance->fNamed["comm_clock_status"] =Register( 0x40000170, 0xFFFFFFFF, 0x00000000, 1 );
547 instance->fNamed["comm_clock_control"] =Register( 0x40000174, 0xFFFFFFFF, 0x00000001, 1 );
548 instance->fNamed["comm_led_config"] =Register( 0x40000180, 0xFFFFFFFF, 0x00000003, 1 );
549 instance->fNamed["comm_led_input"] =Register( 0x40000184, 0xFFFFFFFF, 0xFFFFFFFF, 1 );
550 instance->fNamed["eventDataStatus"] =Register( 0x40000190, 0xFFFFFFFF, 0x00000000, 1 );
551 instance->fNamed["qi_dac_control"] =Register( 0x40000200, 0x00000000, 0x00000001, 1 );
552 instance->fNamed["qi_dac_config"] =Register( 0x40000204, 0x0003FFFF, 0x0003FFFF, 1 );
553 instance->fNamed["bias_control"] =Register( 0x40000300, 0x00000000, 0x00000001, 1 );
554 instance->fNamed["bias_status"] =Register( 0x40000304, 0x00000FFF, 0x00000000, 1 );
555 instance->fNamed["bias_config"] =Register( 0x40000340, 0xFFFFFFFF, 0x00440FFF, 12);
556 instance->fNamed["bias_readback"] =Register( 0x40000380, 0xFFFFFFFF, 0x00000000, 12);
557 instance->fNamed["vmon_config"] =Register( 0x40000400, 0x00FFFFFF, 0x00FFFFFF, 1 );
558 instance->fNamed["vmon_select"] =Register( 0x40000404, 0xFFFFFFFF, 0xFFFFFFFF, 1 );
559 instance->fNamed["vmon_gpio"] =Register( 0x40000408, 0x0000FFFF, 0x0000FFFF, 1 );
560 instance->fNamed["vmon_config_readback"] =Register( 0x40000410, 0x00FFFFFF, 0x00000000, 1 );
561 instance->fNamed["vmon_select_readback"] =Register( 0x40000414, 0xFFFFFFFF, 0x00000000, 1 );
562 instance->fNamed["vmon_gpio_readback"] =Register( 0x40000418, 0x0000FFFF, 0x00000000, 1 );
563 instance->fNamed["vmon_id_readback"] =Register( 0x4000041C, 0x000000FF, 0x00000000, 1 );
564 instance->fNamed["vmon_control"] =Register( 0x40000420, 0x00010100, 0x00010001, 1 );
565 instance->fNamed["vmon_status"] =Register( 0x40000424, 0xFFFFFFFF, 0x00000000, 1 );
566 instance->fNamed["vmon_bias"] =Register( 0x40000440, 0xFFFFFFFF, 0x00000000, 12);
567 instance->fNamed["vmon_value"] =Register( 0x40000480, 0xFFFFFFFF, 0x00000000, 8 );
568 instance->fNamed["imon_config"] =Register( 0x40000500, 0x00FFFFFF, 0x00FFFFFF, 1 );
569 instance->fNamed["imon_select"] =Register( 0x40000504, 0xFFFFFFFF, 0xFFFFFFFF, 1 );
570 instance->fNamed["imon_gpio"] =Register( 0x40000508, 0x0000FFFF, 0x0000FFFF, 1 );
571 instance->fNamed["imon_config_readback"] =Register( 0x40000510, 0x00FFFFFF, 0x00000000, 1 );
572 instance->fNamed["imon_select_readback"] =Register( 0x40000514, 0xFFFFFFFF, 0x00000000, 1 );
573 instance->fNamed["imon_gpio_readback"] =Register( 0x40000518, 0x0000FFFF, 0x00000000, 1 );
574 instance->fNamed["imon_id_readback"] =Register( 0x4000051C, 0x000000FF, 0x00000000, 1 );
575 instance->fNamed["imon_control"] =Register( 0x40000520, 0x00010100, 0x00010001, 1 );
576 instance->fNamed["imon_status"] =Register( 0x40000524, 0xFFFFFFFF, 0x00000000, 1 );
577 instance->fNamed["imon_bias"] =Register( 0x40000540, 0xFFFFFFFF, 0x00000000, 12);
578 instance->fNamed["imon_value"] =Register( 0x40000580, 0xFFFFFFFF, 0x00000000, 8 );
579 instance->fNamed["board_id"] =Register( 0x80000000, 0xFFFFFFFF, 0x00000000, 1 );
580 instance->fNamed["fifo_control"] =Register( 0x80000004, 0xFFFFFFFF, 0x00000000, 1 );
581 instance->fNamed["dp_fpga_fw_build"] =Register( 0x80000010, 0xFFFFFFFF, 0x00000000, 1 );
582 instance->fNamed["calib_build"] =Register( 0x80000014, 0x0FFFFFFF, 0x08000000, 1 );
583 instance->fNamed["dp_clock_status"] =Register( 0x80000020, 0xFFFFFFFF, 0x00000000, 1 );
584 instance->fNamed["module_id"] =Register( 0x80000024, 0x00000FFF, 0x00000FFF, 1 );
585 instance->fNamed["c2c_slave_status"] =Register( 0x80000030, 0xFFFFFFFF, 0x00000000, 1 );
586 instance->fNamed["c2c_slave_intr_control"] =Register( 0x80000034, 0xFFFFFFFF, 0x0000000F, 1 );
587 instance->fNamed["channel_control"] =Register( 0x80000040, 0xFFFFFFFF, 0xFFFFFFFF, 12);
588 instance->fNamed["led_threshold"] =Register( 0x80000080, 0x00FFFFFF, 0x00FFFFFF, 12);
589 instance->fNamed["cfd_parameters"] =Register( 0x800000C0, 0x00001FFF, 0x00001FFF, 12);
590 instance->fNamed["readout_pretrigger"] =Register( 0x80000100, 0x000007FF, 0x000007FF, 12);
591 instance->fNamed["readout_window"] =Register( 0x80000140, 0x000007FE, 0x000007FE, 12);
592 instance->fNamed["p_window"] =Register( 0x80000180, 0x000003FF, 0x000003FF, 12);
593 instance->fNamed["i2_window"] =Register( 0x800001C0, 0x000003FF, 0x000003FF, 12);
594 instance->fNamed["m1_window"] =Register( 0x80000200, 0x000003FF, 0x000003FF, 12);
595 instance->fNamed["m2_window"] =Register( 0x80000240, 0x0000007F, 0x0000007F, 12);
596 instance->fNamed["d_window"] =Register( 0x80000280, 0x0000007F, 0x0000007F, 12);
597 instance->fNamed["i1_window"] =Register( 0x800002C0, 0x000003FF, 0x000003FF, 12);
598 instance->fNamed["disc_width"] =Register( 0x80000300, 0x0000FFFF, 0x0000FFFF, 12);
599 instance->fNamed["baseline_start"] =Register( 0x80000340, 0x00003FFF, 0x00003FFF, 12);
600 instance->fNamed["c_window"] =Register( 0x80000380, 0x00003FFF, 0x00003FFF, 12);
601 instance->fNamed["trigger_input_delay"] =Register( 0x80000400, 0x0000FFFF, 0x0000FFFF, 1 );
602 instance->fNamed["gpio_output_width"] =Register( 0x80000404, 0x0000FFFF, 0x0000FFFF, 1 );
603 instance->fNamed["front_panel_config"] =Register( 0x80000408, 0x00730333, 0x00730333, 1 );
604 instance->fNamed["channel_pulsed_control"] =Register( 0x8000040C, 0x00000000, 0xFFFFFFFF, 1 );
605 instance->fNamed["dsp_led_config"] =Register( 0x80000410, 0xFFFFFFFF, 0x00000003, 1 );
606 instance->fNamed["dsp_led_input"] =Register( 0x80000414, 0xFFFFFFFF, 0xFFFFFFFF, 1 );
607 instance->fNamed["baseline_delay"] =Register( 0x80000418, 0x000000FF, 0x000000FF, 1 );
608 instance->fNamed["diag_channel_input"] =Register( 0x8000041C, 0xFFFFFFFF, 0xFFFFFFFF, 1 );
609 instance->fNamed["event_data_control"] =Register( 0x80000424, 0x00020001, 0x00020001, 1 );
610 instance->fNamed["adc_config"] =Register( 0x80000428, 0xFFFFFFFF, 0xFFFFFFFF, 1 );
611 instance->fNamed["adc_config_load"] =Register( 0x8000042C, 0x00000000, 0x00000001, 1 );
612 instance->fNamed["qi_config"] =Register( 0x80000430, 0x0FFF1F11, 0x0FFF1F11, 1 );
613 instance->fNamed["qi_delay"] =Register( 0x80000434, 0x0000007F, 0x0000007F, 1 );
614 instance->fNamed["qi_pulse_width"] =Register( 0x80000438, 0x0000FFFF, 0x0000FFFF, 1 );
615 instance->fNamed["qi_pulsed"] =Register( 0x8000043C, 0x00000000, 0x00030001, 1 );
616 instance->fNamed["external_gate_width"] =Register( 0x80000440, 0x0000FFFF, 0x0000FFFF, 1 );
617 instance->fNamed["pdts_cmd_control"] =Register( 0x80000460, 0xFFFFFFFF, 0xFFFFFFFF, 3 );
618 instance->fNamed["lat_timestamp_lsb"] =Register( 0x80000484, 0xFFFFFFFF, 0x00000000, 1 );
619 instance->fNamed["lat_timestamp_msb"] =Register( 0x80000488, 0x0000FFFF, 0x00000000, 1 );
620 instance->fNamed["live_timestamp_lsb"] =Register( 0x8000048C, 0xFFFFFFFF, 0x00000000, 1 );
621 instance->fNamed["live_timestamp_msb"] =Register( 0x80000490, 0x0000FFFF, 0x00000000, 1 );
622 instance->fNamed["sync_period"] =Register( 0x80000494, 0xFFFFFFFF, 0x00000000, 1 );
623 instance->fNamed["sync_delay"] =Register( 0x80000498, 0xFFFFFFFF, 0x00000000, 1 );
624 instance->fNamed["sync_count"] =Register( 0x8000049C, 0xFFFFFFFF, 0x00000000, 1 );
625 instance->fNamed["pdts_control"] =Register( 0x800004C0, 0xFFFFFFFF, 0xFFFFFFFF, 1 );
626 instance->fNamed["pdts_status"] =Register( 0x800004C4, 0x00000000, 0xFFFFFFFF, 1 );
627 instance->fNamed["pdts_ts_preset"] =Register( 0x800004C8, 0x00000000, 0xFFFFFFFF, 2 );
628 instance->fNamed["master_logic_control"] =Register( 0x80000500, 0xFFFFFFFF, 0x00000173, 1 );
629 instance->fNamed["master_logic_status"] =Register( 0x80000504, 0x00000001, 0x00000000, 1 );
630 instance->fNamed["overflow_status"] =Register( 0x80000508, 0xFFFFFFFF, 0x00000000, 1 );
631 instance->fNamed["phase_value"] =Register( 0x8000050C, 0xFFFFFFFF, 0x00000000, 1 );
632 instance->fNamed["link_tx_status"] =Register( 0x80000510, 0xFFFFFFFF, 0x00000000, 1 );
633 instance->fNamed["dsp_clock_control"] =Register( 0x80000520, 0x00000713, 0x00000713, 1 );
634 instance->fNamed["dsp_clock_phase_control"] =Register( 0x80000524, 0x00000000, 0x00000007, 1 );
635 instance->fNamed["code_revision"] =Register( 0x80000600, 0xFFFFFFFF, 0x00000000, 1 );
636 instance->fNamed["code_date"] =Register( 0x80000604, 0xFFFFFFFF, 0x00000000, 1 );
637 instance->fNamed["dropped_event_count"] =Register( 0x80000700, 0xFFFFFFFF, 0x00000000, 12);
638 instance->fNamed["accepted_event_count"] =Register( 0x80000740, 0xFFFFFFFF, 0x00000000, 12);
639 instance->fNamed["ahit_count"] =Register( 0x80000780, 0xFFFFFFFF, 0x00000000, 12);
640 instance->fNamed["disc_count"] =Register( 0x800007C0, 0xFFFFFFFF, 0x00000000, 12);
641 instance->fNamed["idelay_count"] =Register( 0x80000800, 0xFFFFFFFF, 0x00000000, 12);
642 instance->fNamed["adc_data_monitor"] =Register( 0x80000840, 0x0000FFFF, 0x00000000, 12);
643 instance->fNamed["adc_status"] =Register( 0x80000880, 0xFFFFFFFF, 0x00000000, 12);
644 // clang-format on
645 }
646 return *instance;
647} // NOLINT(readability/fn_size)
dunedaq::sspmodules::RegMap::c2c_slave_intr_control
unsigned int c2c_slave_intr_control
Definition RegMap.hpp:201
dunedaq::sspmodules::RegMap::d_window
unsigned int d_window[12]
Definition RegMap.hpp:213
dunedaq::sspmodules::RegMap::baseline_start
unsigned int baseline_start[12]
Definition RegMap.hpp:216
dunedaq::sspmodules::RegMap::ahit_count
unsigned int ahit_count[12]
Definition RegMap.hpp:259
dunedaq::sspmodules::RegMap::imon_select_readback
unsigned int imon_select_readback
Definition RegMap.hpp:185
dunedaq::sspmodules::RegMap::qi_dac_control
unsigned int qi_dac_control
Definition RegMap.hpp:161
dunedaq::sspmodules::RegMap::eventDataInterfaceSelect
unsigned int eventDataInterfaceSelect
Definition RegMap.hpp:139
dunedaq::sspmodules::RegMap::front_panel_config
unsigned int front_panel_config
Definition RegMap.hpp:221
dunedaq::sspmodules::RegMap::i2_window
unsigned int i2_window[12]
Definition RegMap.hpp:210
dunedaq::sspmodules::RegMap::dp_clock_status
unsigned int dp_clock_status
Definition RegMap.hpp:198
dunedaq::sspmodules::RegMap::vmon_bias
unsigned int vmon_bias[12]
Definition RegMap.hpp:178
dunedaq::sspmodules::RegMap::armModemStatus
unsigned int armModemStatus
Definition RegMap.hpp:134
dunedaq::sspmodules::RegMap::master_logic_control
unsigned int master_logic_control
Definition RegMap.hpp:246
dunedaq::sspmodules::RegMap::live_timestamp_msb
unsigned int live_timestamp_msb
Definition RegMap.hpp:239
dunedaq::sspmodules::RegMap::dsp_clock_control
unsigned int dsp_clock_control
Definition RegMap.hpp:251
dunedaq::sspmodules::RegMap::eventDataControl
unsigned int eventDataControl
Definition RegMap.hpp:149
dunedaq::sspmodules::RegMap::vmon_value
unsigned int vmon_value[9]
Definition RegMap.hpp:179
dunedaq::sspmodules::RegMap::disc_count
unsigned int disc_count[12]
Definition RegMap.hpp:260
dunedaq::sspmodules::RegMap::lat_timestamp_lsb
unsigned int lat_timestamp_lsb
Definition RegMap.hpp:236
dunedaq::sspmodules::RegMap::master_logic_status
unsigned int master_logic_status
Definition RegMap.hpp:247
dunedaq::sspmodules::RegMap::vmon_config_readback
unsigned int vmon_config_readback
Definition RegMap.hpp:172
dunedaq::sspmodules::RegMap::c_window
unsigned int c_window[12]
Definition RegMap.hpp:217
dunedaq::sspmodules::RegMap::dsp_clock_phase_control
unsigned int dsp_clock_phase_control
Definition RegMap.hpp:252
dunedaq::sspmodules::RegMap::comm_led_config
unsigned int comm_led_config
Definition RegMap.hpp:158
dunedaq::sspmodules::RegMap::codeErrCounts
unsigned int codeErrCounts[5]
Definition RegMap.hpp:146
dunedaq::sspmodules::RegMap::dsp_led_config
unsigned int dsp_led_config
Definition RegMap.hpp:223
dunedaq::sspmodules::RegMap::imon_value
unsigned int imon_value[9]
Definition RegMap.hpp:191
dunedaq::sspmodules::RegMap::pdts_cmd_control
unsigned int pdts_cmd_control[3]
Definition RegMap.hpp:235
dunedaq::sspmodules::RegMap::c2c_master_intr_control
unsigned int c2c_master_intr_control
Definition RegMap.hpp:154
dunedaq::sspmodules::RegMap::armTest
unsigned int armTest[4]
Definition RegMap.hpp:122
dunedaq::sspmodules::RegMap::vmon_gpio_readback
unsigned int vmon_gpio_readback
Definition RegMap.hpp:174
dunedaq::sspmodules::RegMap::channel_control
unsigned int channel_control[12]
Definition RegMap.hpp:203
dunedaq::sspmodules::RegMap::imon_id_readback
unsigned int imon_id_readback
Definition RegMap.hpp:187
dunedaq::sspmodules::RegMap::qi_pulse_width
unsigned int qi_pulse_width
Definition RegMap.hpp:232
dunedaq::sspmodules::RegMap::c2c_master_status
unsigned int c2c_master_status
Definition RegMap.hpp:152
dunedaq::sspmodules::RegMap::event_data_control
unsigned int event_data_control
Definition RegMap.hpp:227
dunedaq::sspmodules::RegMap::accepted_event_count
unsigned int accepted_event_count[12]
Definition RegMap.hpp:258
dunedaq::sspmodules::RegMap::fNamed
std::map< std::string, Register > fNamed
Definition RegMap.hpp:272
dunedaq::sspmodules::RegMap::m2_window
unsigned int m2_window[12]
Definition RegMap.hpp:212
dunedaq::sspmodules::RegMap::i1_window
unsigned int i1_window[12]
Definition RegMap.hpp:214
dunedaq::sspmodules::RegMap::c2c_slave_status
unsigned int c2c_slave_status
Definition RegMap.hpp:200
dunedaq::sspmodules::RegMap::adc_config_load
unsigned int adc_config_load
Definition RegMap.hpp:229
dunedaq::sspmodules::RegMap::trigger_input_delay
unsigned int trigger_input_delay
Definition RegMap.hpp:219
dunedaq::sspmodules::RegMap::timestamp
unsigned int timestamp[2]
Definition RegMap.hpp:145
dunedaq::sspmodules::RegMap::eventDataPhaseControl
unsigned int eventDataPhaseControl
Definition RegMap.hpp:150
dunedaq::sspmodules::RegMap::lat_timestamp_msb
unsigned int lat_timestamp_msb
Definition RegMap.hpp:237
dunedaq::sspmodules::RegMap::external_gate_width
unsigned int external_gate_width
Definition RegMap.hpp:234
dunedaq::sspmodules::RegMap::cfd_parameters
unsigned int cfd_parameters[12]
Definition RegMap.hpp:205
dunedaq::sspmodules::RegMap::dispErrCounts
unsigned int dispErrCounts[5]
Definition RegMap.hpp:147
dunedaq::sspmodules::RegMap::comm_clock_control
unsigned int comm_clock_control
Definition RegMap.hpp:157
dunedaq::sspmodules::RegMap::comm_led_input
unsigned int comm_led_input
Definition RegMap.hpp:159
dunedaq::sspmodules::RegMap::bias_readback
unsigned int bias_readback[12]
Definition RegMap.hpp:167
dunedaq::sspmodules::RegMap::diag_channel_input
unsigned int diag_channel_input
Definition RegMap.hpp:226
dunedaq::sspmodules::RegMap::comm_clock_status
unsigned int comm_clock_status
Definition RegMap.hpp:156
dunedaq::sspmodules::RegMap::imon_bias
unsigned int imon_bias[12]
Definition RegMap.hpp:190
dunedaq::sspmodules::RegMap::adc_status
unsigned int adc_status[12]
Definition RegMap.hpp:263
dunedaq::sspmodules::RegMap::link_rx_status
unsigned int link_rx_status
Definition RegMap.hpp:148
dunedaq::sspmodules::RegMap::eventDataStatus
unsigned int eventDataStatus
Definition RegMap.hpp:160
dunedaq::sspmodules::RegMap::led_threshold
unsigned int led_threshold[12]
Definition RegMap.hpp:204
dunedaq::sspmodules::RegMap::p_window
unsigned int p_window[12]
Definition RegMap.hpp:209
dunedaq::sspmodules::RegMap::adc_data_monitor
unsigned int adc_data_monitor[12]
Definition RegMap.hpp:262
dunedaq::sspmodules::RegMap::gpio_output_width
unsigned int gpio_output_width
Definition RegMap.hpp:220
dunedaq::sspmodules::RegMap::link_tx_status
unsigned int link_tx_status
Definition RegMap.hpp:250
dunedaq::sspmodules::RegMap::vmon_id_readback
unsigned int vmon_id_readback
Definition RegMap.hpp:175
dunedaq::sspmodules::RegMap::zynqTest
unsigned int zynqTest[6]
Definition RegMap.hpp:138
dunedaq::sspmodules::RegMap::idelay_count
unsigned int idelay_count[12]
Definition RegMap.hpp:261
dunedaq::sspmodules::RegMap::channel_pulsed_control
unsigned int channel_pulsed_control
Definition RegMap.hpp:222
dunedaq::sspmodules::RegMap::vmon_select_readback
unsigned int vmon_select_readback
Definition RegMap.hpp:173
dunedaq::sspmodules::RegMap::eventDataPhaseStatus
unsigned int eventDataPhaseStatus
Definition RegMap.hpp:151
dunedaq::sspmodules::RegMap::readout_pretrigger
unsigned int readout_pretrigger[12]
Definition RegMap.hpp:206
dunedaq::sspmodules::RegMap::overflow_status
unsigned int overflow_status
Definition RegMap.hpp:248
dunedaq::sspmodules::RegMap::dp_fpga_fw_build
unsigned int dp_fpga_fw_build
Definition RegMap.hpp:196
dunedaq::sspmodules::RegMap::pdts_ts_preset
unsigned int pdts_ts_preset[2]
Definition RegMap.hpp:245
dunedaq::sspmodules::RegMap::disc_width
unsigned int disc_width[12]
Definition RegMap.hpp:215
dunedaq::sspmodules::RegMap::bias_config
unsigned int bias_config[12]
Definition RegMap.hpp:166
dunedaq::sspmodules::RegMap::imon_gpio_readback
unsigned int imon_gpio_readback
Definition RegMap.hpp:186
dunedaq::sspmodules::RegMap::imon_config_readback
unsigned int imon_config_readback
Definition RegMap.hpp:184
dunedaq::sspmodules::RegMap::baseline_delay
unsigned int baseline_delay
Definition RegMap.hpp:225
dunedaq::sspmodules::RegMap::readout_window
unsigned int readout_window[12]
Definition RegMap.hpp:207
dunedaq::sspmodules::RegMap::m1_window
unsigned int m1_window[12]
Definition RegMap.hpp:211
dunedaq::sspmodules::RegMap::dropped_event_count
unsigned int dropped_event_count[12]
Definition RegMap.hpp:257
dunedaq::sspmodules::RegMap::live_timestamp_lsb
unsigned int live_timestamp_lsb
Definition RegMap.hpp:238

◆ operator=() [1/2]

RegMap & dunedaq::sspmodules::RegMap::operator= ( RegMap && )
privatedelete

◆ operator=() [2/2]

void dunedaq::sspmodules::RegMap::operator= ( RegMap const & )
privatedelete

◆ operator[]()

Register dunedaq::sspmodules::RegMap::operator[] ( std::string name)
inline

Definition at line 108 of file RegMap.hpp.

108 {
109 if(fNamed.find(name)==fNamed.end()){
110 //dune::DAQLogger::LogError("SSP_RegMap")<<"Attempt to access named SSP register "<<name
111 //<<", which does not exist!"<<std::endl;
112 throw(std::invalid_argument(""));
113 }
114 return fNamed[name];
115 }

Member Data Documentation

◆ accepted_event_count

unsigned int dunedaq::sspmodules::RegMap::accepted_event_count[12]

Definition at line 258 of file RegMap.hpp.

◆ adc_config

unsigned int dunedaq::sspmodules::RegMap::adc_config

Definition at line 228 of file RegMap.hpp.

◆ adc_config_load

unsigned int dunedaq::sspmodules::RegMap::adc_config_load

Definition at line 229 of file RegMap.hpp.

◆ adc_data_monitor

unsigned int dunedaq::sspmodules::RegMap::adc_data_monitor[12]

Definition at line 262 of file RegMap.hpp.

◆ adc_status

unsigned int dunedaq::sspmodules::RegMap::adc_status[12]

Definition at line 263 of file RegMap.hpp.

◆ ahit_count

unsigned int dunedaq::sspmodules::RegMap::ahit_count[12]

Definition at line 259 of file RegMap.hpp.

◆ armCommand

unsigned int dunedaq::sspmodules::RegMap::armCommand

Definition at line 120 of file RegMap.hpp.

◆ armError

unsigned int dunedaq::sspmodules::RegMap::armError

Definition at line 119 of file RegMap.hpp.

◆ armModemStatus

unsigned int dunedaq::sspmodules::RegMap::armModemStatus

Definition at line 134 of file RegMap.hpp.

◆ armOperMode

unsigned int dunedaq::sspmodules::RegMap::armOperMode

Definition at line 132 of file RegMap.hpp.

◆ armOptions

unsigned int dunedaq::sspmodules::RegMap::armOptions

Definition at line 133 of file RegMap.hpp.

◆ armPackets

unsigned int dunedaq::sspmodules::RegMap::armPackets

Definition at line 131 of file RegMap.hpp.

◆ armRxAddress

unsigned int dunedaq::sspmodules::RegMap::armRxAddress

Definition at line 123 of file RegMap.hpp.

◆ armRxCommand

unsigned int dunedaq::sspmodules::RegMap::armRxCommand

Definition at line 124 of file RegMap.hpp.

◆ armRxSize

unsigned int dunedaq::sspmodules::RegMap::armRxSize

Definition at line 125 of file RegMap.hpp.

◆ armRxStatus

unsigned int dunedaq::sspmodules::RegMap::armRxStatus

Definition at line 126 of file RegMap.hpp.

◆ armStatus

unsigned int dunedaq::sspmodules::RegMap::armStatus

Definition at line 118 of file RegMap.hpp.

◆ armTest

unsigned int dunedaq::sspmodules::RegMap::armTest[4]

Definition at line 122 of file RegMap.hpp.

◆ armTxAddress

unsigned int dunedaq::sspmodules::RegMap::armTxAddress

Definition at line 127 of file RegMap.hpp.

◆ armTxCommand

unsigned int dunedaq::sspmodules::RegMap::armTxCommand

Definition at line 128 of file RegMap.hpp.

◆ armTxSize

unsigned int dunedaq::sspmodules::RegMap::armTxSize

Definition at line 129 of file RegMap.hpp.

◆ armTxStatus

unsigned int dunedaq::sspmodules::RegMap::armTxStatus

Definition at line 130 of file RegMap.hpp.

◆ armVersion

unsigned int dunedaq::sspmodules::RegMap::armVersion

Definition at line 121 of file RegMap.hpp.

◆ baseline_delay

unsigned int dunedaq::sspmodules::RegMap::baseline_delay

Definition at line 225 of file RegMap.hpp.

◆ baseline_start

unsigned int dunedaq::sspmodules::RegMap::baseline_start[12]

Definition at line 216 of file RegMap.hpp.

◆ bias_config

unsigned int dunedaq::sspmodules::RegMap::bias_config[12]

Definition at line 166 of file RegMap.hpp.

◆ bias_control

unsigned int dunedaq::sspmodules::RegMap::bias_control

Definition at line 164 of file RegMap.hpp.

◆ bias_readback

unsigned int dunedaq::sspmodules::RegMap::bias_readback[12]

Definition at line 167 of file RegMap.hpp.

◆ bias_status

unsigned int dunedaq::sspmodules::RegMap::bias_status

Definition at line 165 of file RegMap.hpp.

◆ board_id

unsigned int dunedaq::sspmodules::RegMap::board_id

Definition at line 194 of file RegMap.hpp.

◆ c2c_control

unsigned int dunedaq::sspmodules::RegMap::c2c_control

Definition at line 153 of file RegMap.hpp.

◆ c2c_master_intr_control

unsigned int dunedaq::sspmodules::RegMap::c2c_master_intr_control

Definition at line 154 of file RegMap.hpp.

◆ c2c_master_status

unsigned int dunedaq::sspmodules::RegMap::c2c_master_status

Definition at line 152 of file RegMap.hpp.

◆ c2c_slave_intr_control

unsigned int dunedaq::sspmodules::RegMap::c2c_slave_intr_control

Definition at line 201 of file RegMap.hpp.

◆ c2c_slave_status

unsigned int dunedaq::sspmodules::RegMap::c2c_slave_status

Definition at line 200 of file RegMap.hpp.

◆ c_window

unsigned int dunedaq::sspmodules::RegMap::c_window[12]

Definition at line 217 of file RegMap.hpp.

◆ calib_build

unsigned int dunedaq::sspmodules::RegMap::calib_build

Definition at line 197 of file RegMap.hpp.

◆ cfd_parameters

unsigned int dunedaq::sspmodules::RegMap::cfd_parameters[12]

Definition at line 205 of file RegMap.hpp.

◆ channel_control

unsigned int dunedaq::sspmodules::RegMap::channel_control[12]

Definition at line 203 of file RegMap.hpp.

◆ channel_pulsed_control

unsigned int dunedaq::sspmodules::RegMap::channel_pulsed_control

Definition at line 222 of file RegMap.hpp.

◆ code_date

unsigned int dunedaq::sspmodules::RegMap::code_date

Definition at line 255 of file RegMap.hpp.

◆ code_revision

unsigned int dunedaq::sspmodules::RegMap::code_revision

Definition at line 254 of file RegMap.hpp.

◆ codeErrCounts

unsigned int dunedaq::sspmodules::RegMap::codeErrCounts[5]

Definition at line 146 of file RegMap.hpp.

◆ comm_clock_control

unsigned int dunedaq::sspmodules::RegMap::comm_clock_control

Definition at line 157 of file RegMap.hpp.

◆ comm_clock_status

unsigned int dunedaq::sspmodules::RegMap::comm_clock_status

Definition at line 156 of file RegMap.hpp.

◆ comm_led_config

unsigned int dunedaq::sspmodules::RegMap::comm_led_config

Definition at line 158 of file RegMap.hpp.

◆ comm_led_input

unsigned int dunedaq::sspmodules::RegMap::comm_led_input

Definition at line 159 of file RegMap.hpp.

◆ d_window

unsigned int dunedaq::sspmodules::RegMap::d_window[12]

Definition at line 213 of file RegMap.hpp.

◆ diag_channel_input

unsigned int dunedaq::sspmodules::RegMap::diag_channel_input

Definition at line 226 of file RegMap.hpp.

◆ disc_count

unsigned int dunedaq::sspmodules::RegMap::disc_count[12]

Definition at line 260 of file RegMap.hpp.

◆ disc_width

unsigned int dunedaq::sspmodules::RegMap::disc_width[12]

Definition at line 215 of file RegMap.hpp.

◆ dispErrCounts

unsigned int dunedaq::sspmodules::RegMap::dispErrCounts[5]

Definition at line 147 of file RegMap.hpp.

◆ dp_clock_status

unsigned int dunedaq::sspmodules::RegMap::dp_clock_status

Definition at line 198 of file RegMap.hpp.

◆ dp_fpga_fw_build

unsigned int dunedaq::sspmodules::RegMap::dp_fpga_fw_build

Definition at line 196 of file RegMap.hpp.

◆ dropped_event_count

unsigned int dunedaq::sspmodules::RegMap::dropped_event_count[12]

Definition at line 257 of file RegMap.hpp.

◆ dsp_clock_control

unsigned int dunedaq::sspmodules::RegMap::dsp_clock_control

Definition at line 251 of file RegMap.hpp.

◆ dsp_clock_phase_control

unsigned int dunedaq::sspmodules::RegMap::dsp_clock_phase_control

Definition at line 252 of file RegMap.hpp.

◆ dsp_led_config

unsigned int dunedaq::sspmodules::RegMap::dsp_led_config

Definition at line 223 of file RegMap.hpp.

◆ dsp_led_input

unsigned int dunedaq::sspmodules::RegMap::dsp_led_input

Definition at line 224 of file RegMap.hpp.

◆ dspStatus

unsigned int dunedaq::sspmodules::RegMap::dspStatus

Definition at line 155 of file RegMap.hpp.

◆ event_data_control

unsigned int dunedaq::sspmodules::RegMap::event_data_control

Definition at line 227 of file RegMap.hpp.

◆ eventDataControl

unsigned int dunedaq::sspmodules::RegMap::eventDataControl

Definition at line 149 of file RegMap.hpp.

◆ eventDataInterfaceSelect

unsigned int dunedaq::sspmodules::RegMap::eventDataInterfaceSelect

Definition at line 139 of file RegMap.hpp.

◆ eventDataPhaseControl

unsigned int dunedaq::sspmodules::RegMap::eventDataPhaseControl

Definition at line 150 of file RegMap.hpp.

◆ eventDataPhaseStatus

unsigned int dunedaq::sspmodules::RegMap::eventDataPhaseStatus

Definition at line 151 of file RegMap.hpp.

◆ eventDataStatus

unsigned int dunedaq::sspmodules::RegMap::eventDataStatus

Definition at line 160 of file RegMap.hpp.

◆ external_gate_width

unsigned int dunedaq::sspmodules::RegMap::external_gate_width

Definition at line 234 of file RegMap.hpp.

◆ fakeBaseline

unsigned int dunedaq::sspmodules::RegMap::fakeBaseline

Definition at line 142 of file RegMap.hpp.

◆ fakeEventSize

unsigned int dunedaq::sspmodules::RegMap::fakeEventSize

Definition at line 141 of file RegMap.hpp.

◆ fakeNumEvents

unsigned int dunedaq::sspmodules::RegMap::fakeNumEvents

Definition at line 140 of file RegMap.hpp.

◆ fakePeakSum

unsigned int dunedaq::sspmodules::RegMap::fakePeakSum

Definition at line 143 of file RegMap.hpp.

◆ fakePrerise

unsigned int dunedaq::sspmodules::RegMap::fakePrerise

Definition at line 144 of file RegMap.hpp.

◆ fifo_control

unsigned int dunedaq::sspmodules::RegMap::fifo_control

Definition at line 195 of file RegMap.hpp.

◆ fNamed

std::map<std::string, Register> dunedaq::sspmodules::RegMap::fNamed
private

Definition at line 272 of file RegMap.hpp.

◆ front_panel_config

unsigned int dunedaq::sspmodules::RegMap::front_panel_config

Definition at line 221 of file RegMap.hpp.

◆ gpio_output_width

unsigned int dunedaq::sspmodules::RegMap::gpio_output_width

Definition at line 220 of file RegMap.hpp.

◆ i1_window

unsigned int dunedaq::sspmodules::RegMap::i1_window[12]

Definition at line 214 of file RegMap.hpp.

◆ i2_window

unsigned int dunedaq::sspmodules::RegMap::i2_window[12]

Definition at line 210 of file RegMap.hpp.

◆ idelay_count

unsigned int dunedaq::sspmodules::RegMap::idelay_count[12]

Definition at line 261 of file RegMap.hpp.

◆ imon_bias

unsigned int dunedaq::sspmodules::RegMap::imon_bias[12]

Definition at line 190 of file RegMap.hpp.

◆ imon_config

unsigned int dunedaq::sspmodules::RegMap::imon_config

Definition at line 181 of file RegMap.hpp.

◆ imon_config_readback

unsigned int dunedaq::sspmodules::RegMap::imon_config_readback

Definition at line 184 of file RegMap.hpp.

◆ imon_control

unsigned int dunedaq::sspmodules::RegMap::imon_control

Definition at line 188 of file RegMap.hpp.

◆ imon_gpio

unsigned int dunedaq::sspmodules::RegMap::imon_gpio

Definition at line 183 of file RegMap.hpp.

◆ imon_gpio_readback

unsigned int dunedaq::sspmodules::RegMap::imon_gpio_readback

Definition at line 186 of file RegMap.hpp.

◆ imon_id_readback

unsigned int dunedaq::sspmodules::RegMap::imon_id_readback

Definition at line 187 of file RegMap.hpp.

◆ imon_select

unsigned int dunedaq::sspmodules::RegMap::imon_select

Definition at line 182 of file RegMap.hpp.

◆ imon_select_readback

unsigned int dunedaq::sspmodules::RegMap::imon_select_readback

Definition at line 185 of file RegMap.hpp.

◆ imon_status

unsigned int dunedaq::sspmodules::RegMap::imon_status

Definition at line 189 of file RegMap.hpp.

◆ imon_value

unsigned int dunedaq::sspmodules::RegMap::imon_value[9]

Definition at line 191 of file RegMap.hpp.

◆ lat_timestamp_lsb

unsigned int dunedaq::sspmodules::RegMap::lat_timestamp_lsb

Definition at line 236 of file RegMap.hpp.

◆ lat_timestamp_msb

unsigned int dunedaq::sspmodules::RegMap::lat_timestamp_msb

Definition at line 237 of file RegMap.hpp.

◆ led_threshold

unsigned int dunedaq::sspmodules::RegMap::led_threshold[12]

Definition at line 204 of file RegMap.hpp.

◆ link_rx_status

unsigned int dunedaq::sspmodules::RegMap::link_rx_status

Definition at line 148 of file RegMap.hpp.

◆ link_tx_status

unsigned int dunedaq::sspmodules::RegMap::link_tx_status

Definition at line 250 of file RegMap.hpp.

◆ live_timestamp_lsb

unsigned int dunedaq::sspmodules::RegMap::live_timestamp_lsb

Definition at line 238 of file RegMap.hpp.

◆ live_timestamp_msb

unsigned int dunedaq::sspmodules::RegMap::live_timestamp_msb

Definition at line 239 of file RegMap.hpp.

◆ m1_window

unsigned int dunedaq::sspmodules::RegMap::m1_window[12]

Definition at line 211 of file RegMap.hpp.

◆ m2_window

unsigned int dunedaq::sspmodules::RegMap::m2_window[12]

Definition at line 212 of file RegMap.hpp.

◆ master_logic_control

unsigned int dunedaq::sspmodules::RegMap::master_logic_control

Definition at line 246 of file RegMap.hpp.

◆ master_logic_status

unsigned int dunedaq::sspmodules::RegMap::master_logic_status

Definition at line 247 of file RegMap.hpp.

◆ module_id

unsigned int dunedaq::sspmodules::RegMap::module_id

Definition at line 199 of file RegMap.hpp.

◆ overflow_status

unsigned int dunedaq::sspmodules::RegMap::overflow_status

Definition at line 248 of file RegMap.hpp.

◆ p_window

unsigned int dunedaq::sspmodules::RegMap::p_window[12]

Definition at line 209 of file RegMap.hpp.

◆ pdts_cmd_control

unsigned int dunedaq::sspmodules::RegMap::pdts_cmd_control[3]

Definition at line 235 of file RegMap.hpp.

◆ pdts_control

unsigned int dunedaq::sspmodules::RegMap::pdts_control

Definition at line 243 of file RegMap.hpp.

◆ pdts_status

unsigned int dunedaq::sspmodules::RegMap::pdts_status

Definition at line 244 of file RegMap.hpp.

◆ pdts_ts_preset

unsigned int dunedaq::sspmodules::RegMap::pdts_ts_preset[2]

Definition at line 245 of file RegMap.hpp.

◆ phase_value

unsigned int dunedaq::sspmodules::RegMap::phase_value

Definition at line 249 of file RegMap.hpp.

◆ PurgeDDR

unsigned int dunedaq::sspmodules::RegMap::PurgeDDR

Definition at line 135 of file RegMap.hpp.

◆ qi_config

unsigned int dunedaq::sspmodules::RegMap::qi_config

Definition at line 230 of file RegMap.hpp.

◆ qi_dac_config

unsigned int dunedaq::sspmodules::RegMap::qi_dac_config

Definition at line 162 of file RegMap.hpp.

◆ qi_dac_control

unsigned int dunedaq::sspmodules::RegMap::qi_dac_control

Definition at line 161 of file RegMap.hpp.

◆ qi_delay

unsigned int dunedaq::sspmodules::RegMap::qi_delay

Definition at line 231 of file RegMap.hpp.

◆ qi_pulse_width

unsigned int dunedaq::sspmodules::RegMap::qi_pulse_width

Definition at line 232 of file RegMap.hpp.

◆ qi_pulsed

unsigned int dunedaq::sspmodules::RegMap::qi_pulsed

Definition at line 233 of file RegMap.hpp.

◆ readout_pretrigger

unsigned int dunedaq::sspmodules::RegMap::readout_pretrigger[12]

Definition at line 206 of file RegMap.hpp.

◆ readout_window

unsigned int dunedaq::sspmodules::RegMap::readout_window[12]

Definition at line 207 of file RegMap.hpp.

◆ sync_count

unsigned int dunedaq::sspmodules::RegMap::sync_count

Definition at line 242 of file RegMap.hpp.

◆ sync_delay

unsigned int dunedaq::sspmodules::RegMap::sync_delay

Definition at line 241 of file RegMap.hpp.

◆ sync_period

unsigned int dunedaq::sspmodules::RegMap::sync_period

Definition at line 240 of file RegMap.hpp.

◆ timestamp

unsigned int dunedaq::sspmodules::RegMap::timestamp[2]

Definition at line 145 of file RegMap.hpp.

◆ trigger_input_delay

unsigned int dunedaq::sspmodules::RegMap::trigger_input_delay

Definition at line 219 of file RegMap.hpp.

◆ vmon_bias

unsigned int dunedaq::sspmodules::RegMap::vmon_bias[12]

Definition at line 178 of file RegMap.hpp.

◆ vmon_config

unsigned int dunedaq::sspmodules::RegMap::vmon_config

Definition at line 169 of file RegMap.hpp.

◆ vmon_config_readback

unsigned int dunedaq::sspmodules::RegMap::vmon_config_readback

Definition at line 172 of file RegMap.hpp.

◆ vmon_control

unsigned int dunedaq::sspmodules::RegMap::vmon_control

Definition at line 176 of file RegMap.hpp.

◆ vmon_gpio

unsigned int dunedaq::sspmodules::RegMap::vmon_gpio

Definition at line 171 of file RegMap.hpp.

◆ vmon_gpio_readback

unsigned int dunedaq::sspmodules::RegMap::vmon_gpio_readback

Definition at line 174 of file RegMap.hpp.

◆ vmon_id_readback

unsigned int dunedaq::sspmodules::RegMap::vmon_id_readback

Definition at line 175 of file RegMap.hpp.

◆ vmon_select

unsigned int dunedaq::sspmodules::RegMap::vmon_select

Definition at line 170 of file RegMap.hpp.

◆ vmon_select_readback

unsigned int dunedaq::sspmodules::RegMap::vmon_select_readback

Definition at line 173 of file RegMap.hpp.

◆ vmon_status

unsigned int dunedaq::sspmodules::RegMap::vmon_status

Definition at line 177 of file RegMap.hpp.

◆ vmon_value

unsigned int dunedaq::sspmodules::RegMap::vmon_value[9]

Definition at line 179 of file RegMap.hpp.

◆ zynqTest

unsigned int dunedaq::sspmodules::RegMap::zynqTest[6]

Definition at line 138 of file RegMap.hpp.

The documentation for this class was generated from the following files:
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