DUNE-DAQ
DUNE Trigger and Data Acquisition software
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Public Member Functions | Private Attributes | Static Private Attributes | List of all members
FE_ASIC_reg_mapping Class Reference

#include <FE_ASIC_reg_mapping.hh>

Public Member Functions

 FE_ASIC_reg_mapping ()
 
void set_ch (uint8_t chip=0, uint8_t chn=0, uint8_t sts=0, uint8_t snc=0, uint8_t sg=0, uint8_t st=0, uint8_t smn=0, uint8_t sdf=0)
 
void set_global (uint8_t chip=0, uint8_t slk0=0, uint8_t stb1=0, uint8_t stb=0, uint8_t s16=0, uint8_t slk1=0, uint8_t sdc=0, uint8_t swdac=0, uint8_t dac=0)
 
void set_chip (uint8_t chip=0, uint8_t sts=0, uint8_t snc=0, uint8_t sg=0, uint8_t st=0, uint8_t smn=0, uint8_t sdf=0, uint8_t slk0=0, uint8_t stb1=0, uint8_t stb=0, uint8_t s16=0, uint8_t slk1=0, uint8_t sdc=0, uint8_t swdac=0, uint8_t dac=0)
 
void set_board (uint8_t sts=0, uint8_t snc=0, uint8_t sg=0, uint8_t st=0, uint8_t smn=0, uint8_t sdf=0, uint8_t slk0=0, uint8_t stb1=0, uint8_t stb=0, uint8_t s16=0, uint8_t slk1=0, uint8_t sdc=0, uint8_t swdac=0, uint8_t dac=0)
 
std::bitset< 1152 > get_bits () const
 
void set_collection_baseline (uint8_t snc)
 
void print () const
 

Private Attributes

std::bitset< 1152 > BITS
 

Static Private Attributes

static const uint8_t channel_wire_plane [8][16]
 

Detailed Description

Definition at line 7 of file FE_ASIC_reg_mapping.hh.

Constructor & Destructor Documentation

◆ FE_ASIC_reg_mapping()

FE_ASIC_reg_mapping::FE_ASIC_reg_mapping ( )

Definition at line 4 of file FE_ASIC_reg_mapping.cpp.

4 : BITS()
5{
6}
FE_ASIC_reg_mapping::BITS
std::bitset< 1152 > BITS
Definition FE_ASIC_reg_mapping.hh:30

Member Function Documentation

◆ get_bits()

std::bitset< 1152 > FE_ASIC_reg_mapping::get_bits ( ) const

Definition at line 73 of file FE_ASIC_reg_mapping.cpp.

74{
75 return BITS;
76}

◆ print()

void FE_ASIC_reg_mapping::print ( ) const

Definition at line 95 of file FE_ASIC_reg_mapping.cpp.

96{
97 std::cout << "FE_ASIC_reg_mapping (binary):" << std::endl;
98 std::string bitString = BITS.to_string<char,std::string::traits_type,std::string::allocator_type>();
99 for(size_t iLine=0; iLine < 36; iLine++)
100 {
101 for(size_t iByte=0; iByte < 4; iByte++)
102 {
103 for(size_t iBit=0; iBit < 8; iBit++)
104 {
105 std::cout << bitString[iLine*32+iByte*8+iBit];
106 }
107 std::cout << ' ';
108 }
109 std::cout << std::endl;
110 }
111 //std::cout << BITS << std::endl;
112}

◆ set_board()

void FE_ASIC_reg_mapping::set_board ( uint8_t sts = 0,
uint8_t snc = 0,
uint8_t sg = 0,
uint8_t st = 0,
uint8_t smn = 0,
uint8_t sdf = 0,
uint8_t slk0 = 0,
uint8_t stb1 = 0,
uint8_t stb = 0,
uint8_t s16 = 0,
uint8_t slk1 = 0,
uint8_t sdc = 0,
uint8_t swdac = 0,
uint8_t dac = 0 )

Definition at line 62 of file FE_ASIC_reg_mapping.cpp.

66{
67 for (size_t chip=0; chip<8; chip++)
68 {
69 set_chip( chip, sts, snc, sg, st, smn, sdf, slk0, stb1, stb, s16, slk1, sdc, swdac, dac);
70 }
71}
FE_ASIC_reg_mapping::set_chip
void set_chip(uint8_t chip=0, uint8_t sts=0, uint8_t snc=0, uint8_t sg=0, uint8_t st=0, uint8_t smn=0, uint8_t sdf=0, uint8_t slk0=0, uint8_t stb1=0, uint8_t stb=0, uint8_t s16=0, uint8_t slk1=0, uint8_t sdc=0, uint8_t swdac=0, uint8_t dac=0)
Definition FE_ASIC_reg_mapping.cpp:49

◆ set_ch()

void FE_ASIC_reg_mapping::set_ch ( uint8_t chip = 0,
uint8_t chn = 0,
uint8_t sts = 0,
uint8_t snc = 0,
uint8_t sg = 0,
uint8_t st = 0,
uint8_t smn = 0,
uint8_t sdf = 0 )

Definition at line 8 of file FE_ASIC_reg_mapping.cpp.

10{
11 unsigned long chn_reg = ((sts&0x01)<<7) + ((snc&0x01)<<6) + ((sg&0x03)<<4)
12 + ((st&0x03)<<2) + ((smn&0x01)<<1) + ((sdf&0x01)<<0);
13 std::bitset<8> bits(chn_reg);
14 size_t start_pos = (8*16+16)*chip + (16-chn)*8;
15 for(size_t iBit=0; iBit < 8; iBit++)
16 {
17 BITS[iBit+start_pos-8] = bits[iBit];
18 }
19}

◆ set_chip()

void FE_ASIC_reg_mapping::set_chip ( uint8_t chip = 0,
uint8_t sts = 0,
uint8_t snc = 0,
uint8_t sg = 0,
uint8_t st = 0,
uint8_t smn = 0,
uint8_t sdf = 0,
uint8_t slk0 = 0,
uint8_t stb1 = 0,
uint8_t stb = 0,
uint8_t s16 = 0,
uint8_t slk1 = 0,
uint8_t sdc = 0,
uint8_t swdac = 0,
uint8_t dac = 0 )

Definition at line 49 of file FE_ASIC_reg_mapping.cpp.

54{
55 for (size_t chn=0; chn<16; chn++)
56 {
57 set_ch(chip, chn, sts, snc, sg, st, smn, sdf);
58 }
59 set_global (chip, slk0, stb1, stb, s16, slk1, sdc, swdac, dac);
60}
FE_ASIC_reg_mapping::set_global
void set_global(uint8_t chip=0, uint8_t slk0=0, uint8_t stb1=0, uint8_t stb=0, uint8_t s16=0, uint8_t slk1=0, uint8_t sdc=0, uint8_t swdac=0, uint8_t dac=0)
Definition FE_ASIC_reg_mapping.cpp:20
FE_ASIC_reg_mapping::set_ch
void set_ch(uint8_t chip=0, uint8_t chn=0, uint8_t sts=0, uint8_t snc=0, uint8_t sg=0, uint8_t st=0, uint8_t smn=0, uint8_t sdf=0)
Definition FE_ASIC_reg_mapping.cpp:8

◆ set_collection_baseline()

void FE_ASIC_reg_mapping::set_collection_baseline ( uint8_t snc)

Definition at line 79 of file FE_ASIC_reg_mapping.cpp.

80{
81 for (size_t chip=0; chip<8; chip++)
82 {
83 for (size_t chn=0; chn<16; chn++)
84 {
85 bool isCollection = (channel_wire_plane[chip][chn] == 2);
86 size_t start_pos = (8*16+16)*chip + (16-chn)*8;
87 if (isCollection)
88 {
89 BITS[6+start_pos-8] = snc & 0x1;
90 }
91 }
92 }
93}
FE_ASIC_reg_mapping::channel_wire_plane
static const uint8_t channel_wire_plane[8][16]
Definition FE_ASIC_reg_mapping.hh:116

◆ set_global()

void FE_ASIC_reg_mapping::set_global ( uint8_t chip = 0,
uint8_t slk0 = 0,
uint8_t stb1 = 0,
uint8_t stb = 0,
uint8_t s16 = 0,
uint8_t slk1 = 0,
uint8_t sdc = 0,
uint8_t swdac = 0,
uint8_t dac = 0 )

Definition at line 20 of file FE_ASIC_reg_mapping.cpp.

23{
24 unsigned long global_reg = ((slk0&0x01)<<0) + ((stb1&0x01)<<1) + ((stb&0x01)<<2)
25 + ((s16&0x01)<<3) + ((slk1&0x01)<<4) + ((sdc&0x01)<<5) +((0&0x03)<<6);
26
27 unsigned long dac_reg = (((dac&0x01)/0x01)<<7)+(((dac&0x02)/0x02)<<6)
28 +(((dac&0x04)/0x04)<<5)+(((dac&0x08)/0x08)<<4)
29 +(((dac&0x10)/0x10)<<3)+(((dac&0x20)/0x20)<<2)
30 +(((swdac&0x03))<<0);
31
32 std::bitset<8> global_bits(global_reg);
33 std::bitset<8> dac_bits(dac_reg);
34
35 std::bitset<16> bits;
36 for(size_t iBit=0; iBit < 8; iBit++)
37 {
38 bits[iBit] = global_bits[iBit];
39 bits[iBit+8] = dac_bits[iBit];
40 }
41
42 size_t start_pos = (8*16+16)*chip + 16*8;
43 for(size_t iBit=0; iBit < 16; iBit++)
44 {
45 BITS[iBit+start_pos] = bits[iBit];
46 }
47}

Member Data Documentation

◆ BITS

std::bitset<1152> FE_ASIC_reg_mapping::BITS
private

Definition at line 30 of file FE_ASIC_reg_mapping.hh.

◆ channel_wire_plane

const uint8_t FE_ASIC_reg_mapping::channel_wire_plane
staticprivate
Initial value:
= {
{0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2},
{0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0},
{2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2},
{0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0},
{2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0}
}

Definition at line 116 of file FE_ASIC_reg_mapping.hh.

The documentation for this class was generated from the following files:
Generated on Sat Jun 28 2025 for DUNE-DAQ by doxygen 1.12.0