FE_ASIC_reg_mapping Class Reference

#include <FE_ASIC_reg_mapping.hh>

Public Member Functions
	FE_ASIC_reg_mapping ()
void	set_ch (uint8_t chip=0, uint8_t chn=0, uint8_t sts=0, uint8_t snc=0, uint8_t sg=0, uint8_t st=0, uint8_t smn=0, uint8_t sdf=0)
void	set_global (uint8_t chip=0, uint8_t slk0=0, uint8_t stb1=0, uint8_t stb=0, uint8_t s16=0, uint8_t slk1=0, uint8_t sdc=0, uint8_t swdac=0, uint8_t dac=0)
void	set_chip (uint8_t chip=0, uint8_t sts=0, uint8_t snc=0, uint8_t sg=0, uint8_t st=0, uint8_t smn=0, uint8_t sdf=0, uint8_t slk0=0, uint8_t stb1=0, uint8_t stb=0, uint8_t s16=0, uint8_t slk1=0, uint8_t sdc=0, uint8_t swdac=0, uint8_t dac=0)
void	set_board (uint8_t sts=0, uint8_t snc=0, uint8_t sg=0, uint8_t st=0, uint8_t smn=0, uint8_t sdf=0, uint8_t slk0=0, uint8_t stb1=0, uint8_t stb=0, uint8_t s16=0, uint8_t slk1=0, uint8_t sdc=0, uint8_t swdac=0, uint8_t dac=0)
std::bitset< 1152 >	get_bits () const
void	set_collection_baseline (uint8_t snc)
void	print () const

Private Attributes
std::bitset< 1152 >	BITS

Static Private Attributes
static const uint8_t	channel_wire_plane [8][16]

Detailed Description

Definition at line 7 of file FE_ASIC_reg_mapping.hh.

Constructor & Destructor Documentation

FE_ASIC_reg_mapping()

FE_ASIC_reg_mapping::FE_ASIC_reg_mapping

(

)

Definition at line 4 of file FE_ASIC_reg_mapping.cpp.

  : BITS()
{
}

Member Function Documentation

get_bits()

std::bitset< 1152 > FE_ASIC_reg_mapping::get_bits

(

)

const

Definition at line 105 of file FE_ASIC_reg_mapping.cpp.

{
  return BITS;
}

print()

void FE_ASIC_reg_mapping::print

(

)

const

Definition at line 125 of file FE_ASIC_reg_mapping.cpp.

{
  std::cout << "FE_ASIC_reg_mapping (binary):" << std::endl;
  std::string bitString = BITS.to_string<char, std::string::traits_type, std::string::allocator_type>();
  for (size_t iLine = 0; iLine < 36; iLine++) {
    for (size_t iByte = 0; iByte < 4; iByte++) {
      for (size_t iBit = 0; iBit < 8; iBit++) {
        std::cout << bitString[iLine * 32 + iByte * 8 + iBit];
      }
      std::cout << ' ';
    }
    std::cout << std::endl;
  }
  // std::cout << BITS << std::endl;
}

set_board()

void FE_ASIC_reg_mapping::set_board	(	uint8_t	sts = 0,
		uint8_t	snc = 0,
		uint8_t	sg = 0,
		uint8_t	st = 0,
		uint8_t	smn = 0,
		uint8_t	sdf = 0,
		uint8_t	slk0 = 0,
		uint8_t	stb1 = 0,
		uint8_t	stb = 0,
		uint8_t	s16 = 0,
		uint8_t	slk1 = 0,
		uint8_t	sdc = 0,
		uint8_t	swdac = 0,
		uint8_t	dac = 0 )

Definition at line 84 of file FE_ASIC_reg_mapping.cpp.

{
  for (size_t chip = 0; chip < 8; chip++) {
    set_chip(chip, sts, snc, sg, st, smn, sdf, slk0, stb1, stb, s16, slk1, sdc, swdac, dac);
  }
}

set_ch()

void FE_ASIC_reg_mapping::set_ch	(	uint8_t	chip = 0,
		uint8_t	chn = 0,
		uint8_t	sts = 0,
		uint8_t	snc = 0,
		uint8_t	sg = 0,
		uint8_t	st = 0,
		uint8_t	smn = 0,
		uint8_t	sdf = 0 )

Definition at line 10 of file FE_ASIC_reg_mapping.cpp.

{
  unsigned long chn_reg = ((sts & 0x01) << 7) + ((snc & 0x01) << 6) + ((sg & 0x03) << 4) + ((st & 0x03) << 2) +
                          ((smn & 0x01) << 1) + ((sdf & 0x01) << 0);
  std::bitset<8> bits(chn_reg);
  size_t start_pos = (8 * 16 + 16) * chip + (16 - chn) * 8;
  for (size_t iBit = 0; iBit < 8; iBit++) {
    BITS[iBit + start_pos - 8] = bits[iBit];
  }
}

set_chip()

void FE_ASIC_reg_mapping::set_chip	(	uint8_t	chip = 0,
		uint8_t	sts = 0,
		uint8_t	snc = 0,
		uint8_t	sg = 0,
		uint8_t	st = 0,
		uint8_t	smn = 0,
		uint8_t	sdf = 0,
		uint8_t	slk0 = 0,
		uint8_t	stb1 = 0,
		uint8_t	stb = 0,
		uint8_t	s16 = 0,
		uint8_t	slk1 = 0,
		uint8_t	sdc = 0,
		uint8_t	swdac = 0,
		uint8_t	dac = 0 )

Definition at line 61 of file FE_ASIC_reg_mapping.cpp.

{
  for (size_t chn = 0; chn < 16; chn++) {
    set_ch(chip, chn, sts, snc, sg, st, smn, sdf);
  }
  set_global(chip, slk0, stb1, stb, s16, slk1, sdc, swdac, dac);
}

set_collection_baseline()

void FE_ASIC_reg_mapping::set_collection_baseline

(

uint8_t

snc

)

Definition at line 111 of file FE_ASIC_reg_mapping.cpp.

{
  for (size_t chip = 0; chip < 8; chip++) {
    for (size_t chn = 0; chn < 16; chn++) {
      bool isCollection = (channel_wire_plane[chip][chn] == 2);
      size_t start_pos = (8 * 16 + 16) * chip + (16 - chn) * 8;
      if (isCollection) {
        BITS[6 + start_pos - 8] = snc & 0x1;
      }
    }
  }
}

set_global()

void FE_ASIC_reg_mapping::set_global	(	uint8_t	chip = 0,
		uint8_t	slk0 = 0,
		uint8_t	stb1 = 0,
		uint8_t	stb = 0,
		uint8_t	s16 = 0,
		uint8_t	slk1 = 0,
		uint8_t	sdc = 0,
		uint8_t	swdac = 0,
		uint8_t	dac = 0 )

Definition at line 28 of file FE_ASIC_reg_mapping.cpp.

{
  unsigned long global_reg = ((slk0 & 0x01) << 0) + ((stb1 & 0x01) << 1) + ((stb & 0x01) << 2) + ((s16 & 0x01) << 3) +
                             ((slk1 & 0x01) << 4) + ((sdc & 0x01) << 5) + ((0 & 0x03) << 6);
 
  unsigned long dac_reg = (((dac & 0x01) / 0x01) << 7) + (((dac & 0x02) / 0x02) << 6) + (((dac & 0x04) / 0x04) << 5) +
                          (((dac & 0x08) / 0x08) << 4) + (((dac & 0x10) / 0x10) << 3) + (((dac & 0x20) / 0x20) << 2) +
                          (((swdac & 0x03)) << 0);
 
  std::bitset<8> global_bits(global_reg);
  std::bitset<8> dac_bits(dac_reg);
 
  std::bitset<16> bits;
  for (size_t iBit = 0; iBit < 8; iBit++) {
    bits[iBit] = global_bits[iBit];
    bits[iBit + 8] = dac_bits[iBit];
  }
 
  size_t start_pos = (8 * 16 + 16) * chip + 16 * 8;
  for (size_t iBit = 0; iBit < 16; iBit++) {
    BITS[iBit + start_pos] = bits[iBit];
  }
}

Member Data Documentation

BITS

std::bitset<1152> FE_ASIC_reg_mapping::BITS

private

Definition at line 30 of file FE_ASIC_reg_mapping.hh.

channel_wire_plane

const uint8_t FE_ASIC_reg_mapping::channel_wire_plane

staticprivate

Initial value:

                                                      = {
  { 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2 }, { 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2 },
  { 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 }, { 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
  { 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2 }, { 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2 },
  { 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 }, { 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 }
}

Definition at line 143 of file FE_ASIC_reg_mapping.hh.

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The documentation for this class was generated from the following files:

• /github/workspace/dunedaq/sourcecode/wibmod/src/wibmod/WIB1/FE_ASIC_reg_mapping.hh
• /github/workspace/dunedaq/sourcecode/wibmod/src/WIB1/FE_ASIC_reg_mapping.cpp