Line data Source code
1 : #include "wibmod/WIB1/FE_ASIC_reg_mapping.hh"
2 : #include <iostream>
3 :
4 0 : FE_ASIC_reg_mapping::FE_ASIC_reg_mapping()
5 0 : : BITS()
6 : {
7 0 : }
8 :
9 : void
10 0 : FE_ASIC_reg_mapping::set_ch(uint8_t chip,
11 : uint8_t chn,
12 : uint8_t sts,
13 : uint8_t snc,
14 : uint8_t sg,
15 : uint8_t st,
16 : uint8_t smn,
17 : uint8_t sdf)
18 : {
19 0 : unsigned long chn_reg = ((sts & 0x01) << 7) + ((snc & 0x01) << 6) + ((sg & 0x03) << 4) + ((st & 0x03) << 2) +
20 0 : ((smn & 0x01) << 1) + ((sdf & 0x01) << 0);
21 0 : std::bitset<8> bits(chn_reg);
22 0 : size_t start_pos = (8 * 16 + 16) * chip + (16 - chn) * 8;
23 0 : for (size_t iBit = 0; iBit < 8; iBit++) {
24 0 : BITS[iBit + start_pos - 8] = bits[iBit];
25 : }
26 0 : }
27 : void
28 0 : FE_ASIC_reg_mapping::set_global(uint8_t chip,
29 : uint8_t slk0,
30 : uint8_t stb1,
31 : uint8_t stb,
32 : uint8_t s16,
33 : uint8_t slk1,
34 : uint8_t sdc,
35 : uint8_t swdac,
36 : uint8_t dac)
37 : {
38 0 : unsigned long global_reg = ((slk0 & 0x01) << 0) + ((stb1 & 0x01) << 1) + ((stb & 0x01) << 2) + ((s16 & 0x01) << 3) +
39 0 : ((slk1 & 0x01) << 4) + ((sdc & 0x01) << 5) + ((0 & 0x03) << 6);
40 :
41 0 : unsigned long dac_reg = (((dac & 0x01) / 0x01) << 7) + (((dac & 0x02) / 0x02) << 6) + (((dac & 0x04) / 0x04) << 5) +
42 0 : (((dac & 0x08) / 0x08) << 4) + (((dac & 0x10) / 0x10) << 3) + (((dac & 0x20) / 0x20) << 2) +
43 0 : (((swdac & 0x03)) << 0);
44 :
45 0 : std::bitset<8> global_bits(global_reg);
46 0 : std::bitset<8> dac_bits(dac_reg);
47 :
48 0 : std::bitset<16> bits;
49 0 : for (size_t iBit = 0; iBit < 8; iBit++) {
50 0 : bits[iBit] = global_bits[iBit];
51 0 : bits[iBit + 8] = dac_bits[iBit];
52 : }
53 :
54 0 : size_t start_pos = (8 * 16 + 16) * chip + 16 * 8;
55 0 : for (size_t iBit = 0; iBit < 16; iBit++) {
56 0 : BITS[iBit + start_pos] = bits[iBit];
57 : }
58 0 : }
59 :
60 : void
61 0 : FE_ASIC_reg_mapping::set_chip(uint8_t chip,
62 : uint8_t sts,
63 : uint8_t snc,
64 : uint8_t sg,
65 : uint8_t st,
66 : uint8_t smn,
67 : uint8_t sdf,
68 : uint8_t slk0,
69 : uint8_t stb1,
70 : uint8_t stb,
71 : uint8_t s16,
72 : uint8_t slk1,
73 : uint8_t sdc,
74 : uint8_t swdac,
75 : uint8_t dac)
76 : {
77 0 : for (size_t chn = 0; chn < 16; chn++) {
78 0 : set_ch(chip, chn, sts, snc, sg, st, smn, sdf);
79 : }
80 0 : set_global(chip, slk0, stb1, stb, s16, slk1, sdc, swdac, dac);
81 0 : }
82 :
83 : void
84 0 : FE_ASIC_reg_mapping::set_board(uint8_t sts,
85 : uint8_t snc,
86 : uint8_t sg,
87 : uint8_t st,
88 : uint8_t smn,
89 : uint8_t sdf,
90 : uint8_t slk0,
91 : uint8_t stb1,
92 : uint8_t stb,
93 : uint8_t s16,
94 : uint8_t slk1,
95 : uint8_t sdc,
96 : uint8_t swdac,
97 : uint8_t dac)
98 : {
99 0 : for (size_t chip = 0; chip < 8; chip++) {
100 0 : set_chip(chip, sts, snc, sg, st, smn, sdf, slk0, stb1, stb, s16, slk1, sdc, swdac, dac);
101 : }
102 0 : }
103 :
104 : std::bitset<1152>
105 0 : FE_ASIC_reg_mapping::get_bits() const
106 : {
107 0 : return BITS;
108 : }
109 :
110 : void
111 0 : FE_ASIC_reg_mapping::set_collection_baseline(uint8_t snc)
112 : {
113 0 : for (size_t chip = 0; chip < 8; chip++) {
114 0 : for (size_t chn = 0; chn < 16; chn++) {
115 0 : bool isCollection = (channel_wire_plane[chip][chn] == 2);
116 0 : size_t start_pos = (8 * 16 + 16) * chip + (16 - chn) * 8;
117 0 : if (isCollection) {
118 0 : BITS[6 + start_pos - 8] = snc & 0x1;
119 : }
120 : }
121 : }
122 0 : }
123 :
124 : void
125 0 : FE_ASIC_reg_mapping::print() const
126 : {
127 0 : std::cout << "FE_ASIC_reg_mapping (binary):" << std::endl;
128 0 : std::string bitString = BITS.to_string<char, std::string::traits_type, std::string::allocator_type>();
129 0 : for (size_t iLine = 0; iLine < 36; iLine++) {
130 0 : for (size_t iByte = 0; iByte < 4; iByte++) {
131 0 : for (size_t iBit = 0; iBit < 8; iBit++) {
132 0 : std::cout << bitString[iLine * 32 + iByte * 8 + iBit];
133 : }
134 0 : std::cout << ' ';
135 : }
136 0 : std::cout << std::endl;
137 : }
138 : // std::cout << BITS << std::endl;
139 0 : }
140 :
141 : // wire plane [asic 0-7][channel 0-15]
142 : // U=0, V=1, W/X/Z/collection=2; increasing in direction electrons drift as larsoft does
143 : const uint8_t FE_ASIC_reg_mapping::channel_wire_plane[8][16] = {
144 : { 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2 }, { 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2 },
145 : { 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 }, { 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
146 : { 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2 }, { 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2 },
147 : { 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 }, { 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 }
148 : };
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