Line data Source code
1 : /**
2 : * @file RegMap.h
3 : *
4 : * This is part of the DUNE DAQ , copyright 2020.
5 : * Licensing/copyright details are in the COPYING file that you should have
6 : * received with this code.
7 : */
8 : #ifndef SSPMODULES_SRC_ANLBOARD_REGMAP_HPP_
9 : #define SSPMODULES_SRC_ANLBOARD_REGMAP_HPP_
10 :
11 :
12 : #include "anlExceptions.hpp"
13 :
14 : #include <iostream>
15 : //#include "dune-artdaq/DAQLogger/DAQLogger.hh"
16 : #include <map>
17 : #include <string>
18 :
19 : namespace dunedaq {
20 : namespace sspmodules {
21 :
22 : //Singleton containing human-readable names for SSP registers.
23 : //Note that Zynq registers are in camelCase, and Artix registers
24 : //are spaced_with_underscores.
25 : class RegMap{
26 : public:
27 :
28 : //Get a reference to the instance of RegMap
29 : static RegMap& Get();
30 :
31 : class Register{
32 : public:
33 0 : Register(unsigned int address, unsigned int readMask, unsigned int writeMask,
34 0 : unsigned int size=1, unsigned int offset=0, unsigned int bits=32):
35 0 : fAddress(address),
36 0 : fReadMask(readMask),
37 0 : fWriteMask(writeMask),
38 0 : fSize(size),
39 0 : fOffset(offset),
40 0 : fBits(bits){}
41 :
42 0 : Register(){}
43 :
44 : //Allow implicit conversion to unsigned int for scalar registers
45 0 : operator unsigned int(){
46 0 : if(fSize>1){
47 : //dune::DAQLogger::LogError("SSP_RegMap")<<"Attempt to access SSP register array at "
48 : // <<std::hex<<fAddress<<std::dec<<" as scalar!"<<std::endl;
49 0 : throw(std::invalid_argument(""));
50 : }
51 0 : return fAddress;
52 : }
53 :
54 : //Indexing returns another register with correct address offset and size 1
55 0 : Register operator[](unsigned int i) const{
56 0 : if(i>=fSize){
57 : //dune::DAQLogger::LogError("SSP_RegMap")<<"Attempt to access SSP register at "
58 : // <<std::hex<<fAddress<<std::dec<<" index "<<i
59 : //<<", beyond end of array (size is "<<fSize<<")"<<std::endl;
60 : }
61 0 : return Register(fAddress+0x4*i,fReadMask,fWriteMask,fOffset,1);
62 : }
63 :
64 : //Getters and setters
65 :
66 0 : inline unsigned int ReadMask() const{
67 0 : return fReadMask;
68 : }
69 :
70 0 : inline unsigned int WriteMask() const{
71 0 : return fWriteMask;
72 : }
73 :
74 : inline unsigned int Offset() const{
75 : return fOffset;
76 : }
77 :
78 : inline unsigned int Bits() const{
79 : return fBits;
80 : }
81 :
82 0 : inline unsigned int Size() const{
83 0 : return fSize;
84 : }
85 :
86 : private:
87 :
88 : //Address of register in SSP space
89 : unsigned int fAddress {0x00000000};
90 :
91 : //Readable/writable bits in this register for calling code to check
92 : //that read/write requests make sense
93 : unsigned int fReadMask {0xFFFFFFFF};
94 : unsigned int fWriteMask {0xFFFFFFFF};
95 :
96 : unsigned int fSize {1};
97 :
98 : //Bit offset of relevant quantity relative to start of addressed word.
99 : //Not currently used but we could use this to "virtually" address logical quantities
100 : //which are assigned only part of a 32-bit word
101 : unsigned int fOffset {0};
102 :
103 : //Number of bits assigned to relevant quantity. Not currently used (see above)
104 : unsigned int fBits {32};
105 : };
106 :
107 : //Get registers using variable names...
108 0 : Register operator[](std::string name){
109 0 : if(fNamed.find(name)==fNamed.end()){
110 : //dune::DAQLogger::LogError("SSP_RegMap")<<"Attempt to access named SSP register "<<name
111 : //<<", which does not exist!"<<std::endl;
112 0 : throw(std::invalid_argument(""));
113 : }
114 0 : return fNamed[name];
115 : }
116 :
117 : // Registers in the ARM Processor
118 : unsigned int armStatus;
119 : unsigned int armError;
120 : unsigned int armCommand;
121 : unsigned int armVersion;
122 : unsigned int armTest[4];
123 : unsigned int armRxAddress; // 0x00000020
124 : unsigned int armRxCommand; // 0x00000024
125 : unsigned int armRxSize; // 0x00000028
126 : unsigned int armRxStatus; // 0x0000002C
127 : unsigned int armTxAddress; // 0x00000030
128 : unsigned int armTxCommand; // 0x00000034
129 : unsigned int armTxSize; // 0x00000038
130 : unsigned int armTxStatus; // 0x0000003C
131 : unsigned int armPackets; // 0x00000040
132 : unsigned int armOperMode; // 0x00000044
133 : unsigned int armOptions; // 0x00000048
134 : unsigned int armModemStatus;// 0x0000004C
135 : unsigned int PurgeDDR; // 0x00000300
136 :
137 : // Registers in the Zynq FPGA
138 : unsigned int zynqTest[6];
139 : unsigned int eventDataInterfaceSelect;
140 : unsigned int fakeNumEvents;
141 : unsigned int fakeEventSize;
142 : unsigned int fakeBaseline;
143 : unsigned int fakePeakSum;
144 : unsigned int fakePrerise;
145 : unsigned int timestamp[2];
146 : unsigned int codeErrCounts[5];
147 : unsigned int dispErrCounts[5];
148 : unsigned int link_rx_status;
149 : unsigned int eventDataControl;
150 : unsigned int eventDataPhaseControl;
151 : unsigned int eventDataPhaseStatus;
152 : unsigned int c2c_master_status;
153 : unsigned int c2c_control;
154 : unsigned int c2c_master_intr_control;
155 : unsigned int dspStatus;
156 : unsigned int comm_clock_status;
157 : unsigned int comm_clock_control;
158 : unsigned int comm_led_config;
159 : unsigned int comm_led_input;
160 : unsigned int eventDataStatus;
161 : unsigned int qi_dac_control;
162 : unsigned int qi_dac_config;
163 :
164 : unsigned int bias_control;
165 : unsigned int bias_status;
166 : unsigned int bias_config[12];
167 : unsigned int bias_readback[12];
168 :
169 : unsigned int vmon_config;
170 : unsigned int vmon_select;
171 : unsigned int vmon_gpio;
172 : unsigned int vmon_config_readback;
173 : unsigned int vmon_select_readback;
174 : unsigned int vmon_gpio_readback;
175 : unsigned int vmon_id_readback;
176 : unsigned int vmon_control;
177 : unsigned int vmon_status;
178 : unsigned int vmon_bias[12];
179 : unsigned int vmon_value[9];
180 :
181 : unsigned int imon_config;
182 : unsigned int imon_select;
183 : unsigned int imon_gpio;
184 : unsigned int imon_config_readback;
185 : unsigned int imon_select_readback;
186 : unsigned int imon_gpio_readback;
187 : unsigned int imon_id_readback;
188 : unsigned int imon_control;
189 : unsigned int imon_status;
190 : unsigned int imon_bias[12];
191 : unsigned int imon_value[9];
192 :
193 : // Registers in the Artix FPGA
194 : unsigned int board_id;
195 : unsigned int fifo_control;
196 : unsigned int dp_fpga_fw_build;
197 : unsigned int calib_build;
198 : unsigned int dp_clock_status;
199 : unsigned int module_id;
200 : unsigned int c2c_slave_status;
201 : unsigned int c2c_slave_intr_control;
202 :
203 : unsigned int channel_control[12];
204 : unsigned int led_threshold[12];
205 : unsigned int cfd_parameters[12];
206 : unsigned int readout_pretrigger[12];
207 : unsigned int readout_window[12];
208 :
209 : unsigned int p_window[12];
210 : unsigned int i2_window[12];
211 : unsigned int m1_window[12];
212 : unsigned int m2_window[12];
213 : unsigned int d_window[12];
214 : unsigned int i1_window[12];
215 : unsigned int disc_width[12];
216 : unsigned int baseline_start[12];
217 : unsigned int c_window[12];
218 :
219 : unsigned int trigger_input_delay;
220 : unsigned int gpio_output_width;
221 : unsigned int front_panel_config;
222 : unsigned int channel_pulsed_control;
223 : unsigned int dsp_led_config;
224 : unsigned int dsp_led_input;
225 : unsigned int baseline_delay;
226 : unsigned int diag_channel_input;
227 : unsigned int event_data_control;
228 : unsigned int adc_config;
229 : unsigned int adc_config_load;
230 : unsigned int qi_config;
231 : unsigned int qi_delay;
232 : unsigned int qi_pulse_width;
233 : unsigned int qi_pulsed;
234 : unsigned int external_gate_width;
235 : unsigned int pdts_cmd_control[3];
236 : unsigned int lat_timestamp_lsb;
237 : unsigned int lat_timestamp_msb;
238 : unsigned int live_timestamp_lsb;
239 : unsigned int live_timestamp_msb;
240 : unsigned int sync_period;
241 : unsigned int sync_delay;
242 : unsigned int sync_count;
243 : unsigned int pdts_control;
244 : unsigned int pdts_status;
245 : unsigned int pdts_ts_preset[2];
246 : unsigned int master_logic_control;
247 : unsigned int master_logic_status;
248 : unsigned int overflow_status;
249 : unsigned int phase_value;
250 : unsigned int link_tx_status;
251 : unsigned int dsp_clock_control;
252 : unsigned int dsp_clock_phase_control;
253 :
254 : unsigned int code_revision;
255 : unsigned int code_date;
256 :
257 : unsigned int dropped_event_count[12];
258 : unsigned int accepted_event_count[12];
259 : unsigned int ahit_count[12];
260 : unsigned int disc_count[12];
261 : unsigned int idelay_count[12];
262 : unsigned int adc_data_monitor[12];
263 : unsigned int adc_status[12];
264 :
265 : private:
266 0 : RegMap(){}
267 : ~RegMap(){}
268 : RegMap(RegMap const&) = delete; //Don't implement
269 : void operator=(RegMap const&) = delete; //Don't implement
270 : RegMap(RegMap&&) = delete;
271 : RegMap& operator=(RegMap&&) = delete;
272 : std::map<std::string, Register> fNamed;
273 : };
274 :
275 : } // namespace sspmodules
276 : } // namespace dunedaq
277 :
278 : #endif // SSPMODULES_SRC_ANLBOARD_REGMAP_HPP_
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