Line data Source code
1 : /**
2 : * @file RegMap.h
3 : *
4 : * This is part of the DUNE DAQ , copyright 2020.
5 : * Licensing/copyright details are in the COPYING file that you should have
6 : * received with this code.
7 : */
8 : #ifndef SSPMODULES_SRC_ANLBOARD_REGMAP_HPP_
9 : #define SSPMODULES_SRC_ANLBOARD_REGMAP_HPP_
10 :
11 : #include "anlExceptions.hpp"
12 :
13 : #include <iostream>
14 : // #include "dune-artdaq/DAQLogger/DAQLogger.hh"
15 : #include <map>
16 : #include <string>
17 :
18 : namespace dunedaq {
19 : namespace sspmodules {
20 :
21 : // Singleton containing human-readable names for SSP registers.
22 : // Note that Zynq registers are in camelCase, and Artix registers
23 : // are spaced_with_underscores.
24 : class RegMap
25 : {
26 : public:
27 : // Get a reference to the instance of RegMap
28 : static RegMap& Get();
29 :
30 : class Register
31 : {
32 : public:
33 0 : Register(unsigned int address,
34 : unsigned int readMask,
35 : unsigned int writeMask,
36 : unsigned int size = 1,
37 : unsigned int offset = 0,
38 : unsigned int bits = 32)
39 0 : : fAddress(address)
40 0 : , fReadMask(readMask)
41 0 : , fWriteMask(writeMask)
42 0 : , fSize(size)
43 0 : , fOffset(offset)
44 0 : , fBits(bits)
45 : {
46 0 : }
47 :
48 0 : Register() {}
49 :
50 : // Allow implicit conversion to unsigned int for scalar registers
51 0 : operator unsigned int()
52 : {
53 0 : if (fSize > 1) {
54 : // dune::DAQLogger::LogError("SSP_RegMap")<<"Attempt to access SSP register array at "
55 : // <<std::hex<<fAddress<<std::dec<<" as scalar!"<<std::endl;
56 0 : throw(std::invalid_argument(""));
57 : }
58 0 : return fAddress;
59 : }
60 :
61 : // Indexing returns another register with correct address offset and size 1
62 0 : Register operator[](unsigned int i) const
63 : {
64 0 : if (i >= fSize) {
65 : // dune::DAQLogger::LogError("SSP_RegMap")<<"Attempt to access SSP register at "
66 : // <<std::hex<<fAddress<<std::dec<<" index "<<i
67 : //<<", beyond end of array (size is "<<fSize<<")"<<std::endl;
68 : }
69 0 : return Register(fAddress + 0x4 * i, fReadMask, fWriteMask, fOffset, 1);
70 : }
71 :
72 : // Getters and setters
73 :
74 0 : inline unsigned int ReadMask() const { return fReadMask; }
75 :
76 0 : inline unsigned int WriteMask() const { return fWriteMask; }
77 :
78 : inline unsigned int Offset() const { return fOffset; }
79 :
80 : inline unsigned int Bits() const { return fBits; }
81 :
82 0 : inline unsigned int Size() const { return fSize; }
83 :
84 : private:
85 : // Address of register in SSP space
86 : unsigned int fAddress{ 0x00000000 };
87 :
88 : // Readable/writable bits in this register for calling code to check
89 : // that read/write requests make sense
90 : unsigned int fReadMask{ 0xFFFFFFFF };
91 : unsigned int fWriteMask{ 0xFFFFFFFF };
92 :
93 : unsigned int fSize{ 1 };
94 :
95 : // Bit offset of relevant quantity relative to start of addressed word.
96 : // Not currently used but we could use this to "virtually" address logical quantities
97 : // which are assigned only part of a 32-bit word
98 : unsigned int fOffset{ 0 };
99 :
100 : // Number of bits assigned to relevant quantity. Not currently used (see above)
101 : unsigned int fBits{ 32 };
102 : };
103 :
104 : // Get registers using variable names...
105 0 : Register operator[](std::string name)
106 : {
107 0 : if (fNamed.find(name) == fNamed.end()) {
108 : // dune::DAQLogger::LogError("SSP_RegMap")<<"Attempt to access named SSP register "<<name
109 : //<<", which does not exist!"<<std::endl;
110 0 : throw(std::invalid_argument(""));
111 : }
112 0 : return fNamed[name];
113 : }
114 :
115 : // Registers in the ARM Processor
116 : unsigned int armStatus;
117 : unsigned int armError;
118 : unsigned int armCommand;
119 : unsigned int armVersion;
120 : unsigned int armTest[4];
121 : unsigned int armRxAddress; // 0x00000020
122 : unsigned int armRxCommand; // 0x00000024
123 : unsigned int armRxSize; // 0x00000028
124 : unsigned int armRxStatus; // 0x0000002C
125 : unsigned int armTxAddress; // 0x00000030
126 : unsigned int armTxCommand; // 0x00000034
127 : unsigned int armTxSize; // 0x00000038
128 : unsigned int armTxStatus; // 0x0000003C
129 : unsigned int armPackets; // 0x00000040
130 : unsigned int armOperMode; // 0x00000044
131 : unsigned int armOptions; // 0x00000048
132 : unsigned int armModemStatus; // 0x0000004C
133 : unsigned int PurgeDDR; // 0x00000300
134 :
135 : // Registers in the Zynq FPGA
136 : unsigned int zynqTest[6];
137 : unsigned int eventDataInterfaceSelect;
138 : unsigned int fakeNumEvents;
139 : unsigned int fakeEventSize;
140 : unsigned int fakeBaseline;
141 : unsigned int fakePeakSum;
142 : unsigned int fakePrerise;
143 : unsigned int timestamp[2];
144 : unsigned int codeErrCounts[5];
145 : unsigned int dispErrCounts[5];
146 : unsigned int link_rx_status;
147 : unsigned int eventDataControl;
148 : unsigned int eventDataPhaseControl;
149 : unsigned int eventDataPhaseStatus;
150 : unsigned int c2c_master_status;
151 : unsigned int c2c_control;
152 : unsigned int c2c_master_intr_control;
153 : unsigned int dspStatus;
154 : unsigned int comm_clock_status;
155 : unsigned int comm_clock_control;
156 : unsigned int comm_led_config;
157 : unsigned int comm_led_input;
158 : unsigned int eventDataStatus;
159 : unsigned int qi_dac_control;
160 : unsigned int qi_dac_config;
161 :
162 : unsigned int bias_control;
163 : unsigned int bias_status;
164 : unsigned int bias_config[12];
165 : unsigned int bias_readback[12];
166 :
167 : unsigned int vmon_config;
168 : unsigned int vmon_select;
169 : unsigned int vmon_gpio;
170 : unsigned int vmon_config_readback;
171 : unsigned int vmon_select_readback;
172 : unsigned int vmon_gpio_readback;
173 : unsigned int vmon_id_readback;
174 : unsigned int vmon_control;
175 : unsigned int vmon_status;
176 : unsigned int vmon_bias[12];
177 : unsigned int vmon_value[9];
178 :
179 : unsigned int imon_config;
180 : unsigned int imon_select;
181 : unsigned int imon_gpio;
182 : unsigned int imon_config_readback;
183 : unsigned int imon_select_readback;
184 : unsigned int imon_gpio_readback;
185 : unsigned int imon_id_readback;
186 : unsigned int imon_control;
187 : unsigned int imon_status;
188 : unsigned int imon_bias[12];
189 : unsigned int imon_value[9];
190 :
191 : // Registers in the Artix FPGA
192 : unsigned int board_id;
193 : unsigned int fifo_control;
194 : unsigned int dp_fpga_fw_build;
195 : unsigned int calib_build;
196 : unsigned int dp_clock_status;
197 : unsigned int module_id;
198 : unsigned int c2c_slave_status;
199 : unsigned int c2c_slave_intr_control;
200 :
201 : unsigned int channel_control[12];
202 : unsigned int led_threshold[12];
203 : unsigned int cfd_parameters[12];
204 : unsigned int readout_pretrigger[12];
205 : unsigned int readout_window[12];
206 :
207 : unsigned int p_window[12];
208 : unsigned int i2_window[12];
209 : unsigned int m1_window[12];
210 : unsigned int m2_window[12];
211 : unsigned int d_window[12];
212 : unsigned int i1_window[12];
213 : unsigned int disc_width[12];
214 : unsigned int baseline_start[12];
215 : unsigned int c_window[12];
216 :
217 : unsigned int trigger_input_delay;
218 : unsigned int gpio_output_width;
219 : unsigned int front_panel_config;
220 : unsigned int channel_pulsed_control;
221 : unsigned int dsp_led_config;
222 : unsigned int dsp_led_input;
223 : unsigned int baseline_delay;
224 : unsigned int diag_channel_input;
225 : unsigned int event_data_control;
226 : unsigned int adc_config;
227 : unsigned int adc_config_load;
228 : unsigned int qi_config;
229 : unsigned int qi_delay;
230 : unsigned int qi_pulse_width;
231 : unsigned int qi_pulsed;
232 : unsigned int external_gate_width;
233 : unsigned int pdts_cmd_control[3];
234 : unsigned int lat_timestamp_lsb;
235 : unsigned int lat_timestamp_msb;
236 : unsigned int live_timestamp_lsb;
237 : unsigned int live_timestamp_msb;
238 : unsigned int sync_period;
239 : unsigned int sync_delay;
240 : unsigned int sync_count;
241 : unsigned int pdts_control;
242 : unsigned int pdts_status;
243 : unsigned int pdts_ts_preset[2];
244 : unsigned int master_logic_control;
245 : unsigned int master_logic_status;
246 : unsigned int overflow_status;
247 : unsigned int phase_value;
248 : unsigned int link_tx_status;
249 : unsigned int dsp_clock_control;
250 : unsigned int dsp_clock_phase_control;
251 :
252 : unsigned int code_revision;
253 : unsigned int code_date;
254 :
255 : unsigned int dropped_event_count[12];
256 : unsigned int accepted_event_count[12];
257 : unsigned int ahit_count[12];
258 : unsigned int disc_count[12];
259 : unsigned int idelay_count[12];
260 : unsigned int adc_data_monitor[12];
261 : unsigned int adc_status[12];
262 :
263 : private:
264 0 : RegMap() {}
265 : ~RegMap() {}
266 : RegMap(RegMap const&) = delete; // Don't implement
267 : void operator=(RegMap const&) = delete; // Don't implement
268 : RegMap(RegMap&&) = delete;
269 : RegMap& operator=(RegMap&&) = delete;
270 : std::map<std::string, Register> fNamed;
271 : };
272 :
273 : } // namespace sspmodules
274 : } // namespace dunedaq
275 :
276 : #endif // SSPMODULES_SRC_ANLBOARD_REGMAP_HPP_
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